Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

Conflicts:
	wally-pipelined/src/ifu/ifu.sv

wally-pipelined/src/fpu/fpu.sv

@@ -41,8 +41,8 @@ module fpu (
 
   //temporarily assign pipe clear and enable signals
   //to never flush & always be running
-  assign PipeClear = 1'b0;
+  localparam PipeClear = 1'b0;
-  assign PipeEnable = 1'b1;
+  localparam PipeEnable = 1'b1;
   always_comb begin
 
 	  PipeEnableDE = PipeEnable;
@@ -154,6 +154,7 @@ module fpu (
   logic [10:0]             AddExpPostSumE;
   logic                    AddCorrSignE, AddOp1NormE, AddOp2NormE, AddOpANormE, AddOpBNormE, AddInvalidE;
   logic                    AddDenormInE, AddSwapE, AddNormOvflowE, AddSignAE;
+  logic                    AddConvertE;
   logic [63:0]             AddFloat1E, AddFloat2E;
   logic [10:0]             AddExp1DenormE, AddExp2DenormE, AddExponentE;
   logic [63:0]             AddOp1E, AddOp2E;
@@ -310,6 +311,7 @@ module fpu (
   logic [10:0]             AddExpPostSumM;
   logic                    AddCorrSignM, AddOp1NormM, AddOp2NormM, AddOpANormM, AddOpBNormM, AddInvalidM;
   logic                    AddDenormInM, AddSwapM, AddNormOvflowM, AddSignAM;
+  logic                    AddConvertM, AddSignM;
   logic [63:0]             AddFloat1M, AddFloat2M;
   logic [10:0]             AddExp1DenormM, AddExp2DenormM, AddExponentM;
   logic [63:0]             AddOp1M, AddOp2M;

wally-pipelined/src/fpu/fpuaddcvt2.sv

@@ -64,6 +64,7 @@ module fpuaddcvt2 (AddResultM, AddFlagsM, AddDenormM, AddSumM, AddSumTcM, AddSel
    wire [63:0] 	 Result;   
    wire [63:0] 	 sum_norm, sum_norm_w_bypass;
    wire [5:0] 	 norm_shift, norm_shift_denorm;
+   wire          exp_valid;
    wire		 DenormIO;
    wire [4:0] 	 FlagsIn;	
    wire 	 Sticky_out;

wally-pipelined/src/ifu/icache.sv

@@ -57,7 +57,7 @@ module icache(
     logic [`XLEN-1:0] LastReadDataF, LastReadAdrF, InDataF;
 
     // instruction for NOP
-    logic [31:0]      nop = 32'h00000013;
+    localparam [31:0]      nop = 32'h00000013;
 
     // Temporary change to bridge the new interface to old behaviors
     logic [`XLEN-1:0] PCPF;

wally-pipelined/src/ifu/ifu.sv

@@ -75,7 +75,7 @@ module ifu (
   logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkM, PCPF;
   logic             CompressedF;
   logic [31:0]      InstrRawD, InstrE, InstrW;
-  logic [31:0]      nop = 32'h00000013; // instruction for NOP
+  localparam [31:0]      nop = 32'h00000013; // instruction for NOP
 
   tlb #(.ENTRY_BITS(3), .ITLB(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF),
                 .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),

wally-pipelined/src/muldiv/div.sv

@@ -47,6 +47,7 @@ module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start);
    logic [3:0] 	       quotient;
    logic 	       otfzero; 
    logic 	       shiftResult;
+   logic           enablev, state0v, donev, divdonev, oftzerov, divBusyv, ulp;
 
    // Divider goes the distance to 37 cycles
    // (thanks the evil divisor for D = 0x1) 

wally-pipelined/src/muldiv/muldiv.sv

@@ -55,6 +55,7 @@ module muldiv (
 	logic 		     enable_q, gclk;
 
 	logic [2:0] 	     Funct3E_Q;
+    logic            div0error;
 
 
 	 // Multiplier

wally-pipelined/testbench/testbench-busybear.sv

@@ -299,11 +299,13 @@ module testbench_busybear();
             `ERROR \
           end \
         end else begin \
-          for(integer j=0; j<totalCSR; j++) begin \
+          if (!(`BUILDROOT == 1 && "MSTATUS" == `"CSR`")) begin \
-            if(!StartCSRname[j].icompare(`"CSR`")) begin \
+            for(integer j=0; j<totalCSR; j++) begin \
-              if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
+              if(!StartCSRname[j].icompare(`"CSR`")) begin \
-                $display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
+                if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
-                `ERROR \
+                  $display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
+                  `ERROR \
+                end \
               end \
             end \
           end \