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controlleres and zbb handle byte instructions

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This commit is contained in:
Kevin Kim 2023-02-18 21:06:55 -08:00
parent 27581f8d28
commit 888f4318bc
3 changed files with 17 additions and 6 deletions
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9
src/ieu/bmu/bmuctrl.sv
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@ -132,6 +132,15 @@ module bmuctrl(
17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111; // andn 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111; // andn
17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111; // orn 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111; // orn
17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111; // xnor 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111; // xnor
17'b0010011_0110101_101: if (`XLEN == 64)
BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv64)
else
BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction
17'b0010011_0110100_101: if (`XLEN == 32)
BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv32)
else
BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction
17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011; // orc.b
default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift
endcase endcase

8
src/ieu/bmu/byte.sv
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@ -30,10 +30,10 @@
`include "wally-config.vh" `include "wally-config.vh"
module byteUnit #(parameter WIDTH=32) ( module byteUnit #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, // Operands input logic [WIDTH-1:0] A, B, // Operands
output logic [WIDTH-1:0] OrcBResult, // OrcB result output logic [WIDTH-1:0] ByteResult); // rev8, orcb result
output logic [WIDTH-1:0] Rev8Result); // Rev8 result
logic [WIDTH-1:0] OrcBResult, Rev8Result;
genvar i; genvar i;
for (i=0;i<WIDTH;i+=8) begin:loop for (i=0;i<WIDTH;i+=8) begin:loop
@ -41,4 +41,6 @@ module byteUnit #(parameter WIDTH=32) (
assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i]; assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
end end
assign ByteResult = (B[0]) ? OrcBResult : Rev8Result;
endmodule endmodule

6
src/ieu/bmu/zbb.sv
View File

@ -43,14 +43,13 @@ module zbb #(parameter WIDTH=32) (
logic [WIDTH-1:0] CntResult; logic [WIDTH-1:0] CntResult;
// byte results // byte results
logic [WIDTH-1:0] OrcBResult; logic [WIDTH-1:0] ByteResult;
logic [WIDTH-1:0] Rev8Result;
// sign/zero extend results // sign/zero extend results
logic [WIDTH-1:0] ExtResult; // sign/zero extend result logic [WIDTH-1:0] ExtResult; // sign/zero extend result
cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult));
byteUnit #(WIDTH) bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result)); byteUnit #(WIDTH) bu(.A(A), .B(B), .ByteResult(ByteResult));
ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult));
//can replace with structural mux by looking at bit 4 in rs2 field //can replace with structural mux by looking at bit 4 in rs2 field
@ -59,6 +58,7 @@ module zbb #(parameter WIDTH=32) (
3'b111: ZBBResult = ALUResult; // rotates, andn, xnor, orn 3'b111: ZBBResult = ALUResult; // rotates, andn, xnor, orn
3'b000: ZBBResult = CntResult; // count 3'b000: ZBBResult = CntResult; // count
3'b100: ZBBResult = ExtResult; // sign/zero extend 3'b100: ZBBResult = ExtResult; // sign/zero extend
3'b011: ZBBResult = ByteResult; // byte instructions
/*15'b0010100_101_00111: ZBBResult = OrcBResult; /*15'b0010100_101_00111: ZBBResult = OrcBResult;
15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110100_101_11000: ZBBResult = Rev8Result;
15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result;