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Removed amo logic from ahblite. Removed many unused signals from ahblite.

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This commit is contained in:
Ross Thompson 2021-08-25 22:45:13 -05:00
parent 596bc138bc
commit 8836d91896
3 changed files with 2 additions and 35 deletions
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33
wally-pipelined/src/ebu/ahblite.sv
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@ -69,9 +69,7 @@ module ahblite (
// Delayed signals for writes // Delayed signals for writes
output logic [2:0] HADDRD, output logic [2:0] HADDRD,
output logic [3:0] HSIZED, output logic [3:0] HSIZED,
output logic HWRITED, output logic HWRITED
// Stalls
output logic CommitM
); );
logic GrantData; logic GrantData;
@ -141,7 +139,7 @@ module ahblite (
assign HMASTLOCK = 0; // no locking supported assign HMASTLOCK = 0; // no locking supported
assign HWRITE = (NextBusState == MEMWRITE) || (NextBusState == ATOMICWRITE); assign HWRITE = (NextBusState == MEMWRITE) || (NextBusState == ATOMICWRITE);
// delay write data by one cycle for // delay write data by one cycle for
flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN flop #(`XLEN) wdreg(HCLK, DCtoAHBWriteData, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
// delay signals for subword writes // delay signals for subword writes
flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
@ -154,33 +152,6 @@ module ahblite (
assign InstrRData = HRDATA; assign InstrRData = HRDATA;
assign DCfromAHBReadData = HRDATA; assign DCfromAHBReadData = HRDATA;
assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD); assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
assign CommitM = (BusState == MEMREAD) || (BusState == MEMWRITE) || (BusState == ATOMICREAD) || (BusState == ATOMICWRITE);
assign DCfromAHBAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE); assign DCfromAHBAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
// Carefully decide when to update ReadDataW
// ReadDataMstored holds the most recent memory read.
// We need to wait until the pipeline actually advances before we can update the contents of ReadDataW
// (or else the W stage will accidentally get the M stage's data when the pipeline does advance).
assign CaptureDataM = ((BusState == MEMREAD) && (NextBusState != MEMREAD)) ||
((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD));
flopenr #(`XLEN) ReadDataNewWReg(clk, reset, CaptureDataM, HRDATAMasked, CapturedHRDATAMasked);
always @(posedge HCLK, negedge HRESETn)
if (~HRESETn)
CapturedDataAvailable <= #1 1'b0;
else
CapturedDataAvailable <= #1 (StallW) ? (CaptureDataM | CapturedDataAvailable) : 1'b0;
// *** AMO portion will go away when it is moved into the LSU
// Handle AMO instructions if applicable
generate
if (`A_SUPPORTED) begin
logic [`XLEN-1:0] AMOResult;
logic [`XLEN-1:0] HRDATAW;
amoalu amoalu(.srca(HRDATAW), .srcb(DCtoAHBWriteData), .funct(Funct7M), .width(MemSizeM),
.result(AMOResult));
mux2 #(`XLEN) wdmux(DCtoAHBWriteData, AMOResult, AtomicMaskedM[1], WriteData);
end else
assign WriteData = DCtoAHBWriteData;
endgenerate
endmodule endmodule

1
wally-pipelined/src/lsu/lsu.sv
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@ -64,7 +64,6 @@ module lsu
output logic StoreMisalignedFaultM, StoreAccessFaultM, output logic StoreMisalignedFaultM, StoreAccessFaultM,
// connect to ahb // connect to ahb
input logic CommitM, // should this be generated in the abh interface?
output logic [`PA_BITS-1:0] DCtoAHBPAdrM, output logic [`PA_BITS-1:0] DCtoAHBPAdrM,
output logic DCtoAHBReadM, output logic DCtoAHBReadM,
output logic DCtoAHBWriteM, output logic DCtoAHBWriteM,

3
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -152,8 +152,6 @@ module wallypipelinedhart
logic [`XLEN-1:0] DCfromAHBReadData; logic [`XLEN-1:0] DCfromAHBReadData;
logic [`XLEN-1:0] DCtoAHBWriteData; logic [`XLEN-1:0] DCtoAHBWriteData;
logic CommitM;
logic BPPredWrongE; logic BPPredWrongE;
logic BPPredDirWrongM; logic BPPredDirWrongM;
logic BTBPredPCWrongM; logic BTBPredPCWrongM;
@ -200,7 +198,6 @@ module wallypipelinedhart
.ReadDataM(ReadDataM), .ReadDataM(ReadDataM),
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.CommitM(CommitM),
.DCtoAHBPAdrM(DCtoAHBPAdrM), .DCtoAHBPAdrM(DCtoAHBPAdrM),
.DCtoAHBReadM(DCtoAHBReadM), .DCtoAHBReadM(DCtoAHBReadM),
.DCtoAHBWriteM(DCtoAHBWriteM), .DCtoAHBWriteM(DCtoAHBWriteM),