diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do
index e6d9a37aa..9a3039afa 100644
--- a/sim/coverage-exclusions-rv64gc.do
+++ b/sim/coverage-exclusions-rv64gc.do
@@ -323,6 +323,29 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefs
 set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"]
 coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
 
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 4
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 3
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 5
+
 # TLB not recently used never has all RU bits = 1 because it will then clear all to 0
 # This is a blunt instrument; perhaps there is a more graceful exclusion
 coverage exclude -srcfile priorityonehot.sv 
diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
index fdc088a10..4f2965474 100644
--- a/src/ebu/buscachefsm.sv
+++ b/src/ebu/buscachefsm.sv
@@ -87,12 +87,12 @@ module buscachefsm #(
   
   always_comb begin
       case(CurrState)
-        ADR_PHASE: if (HREADY & |BusRW)                               NextState = DATA_PHASE;
-                   else if (HREADY & BusWrite)                        NextState = CACHE_WRITEBACK;
+        ADR_PHASE: if (HREADY & |BusRW)                               NextState = DATA_PHASE; // exclusion-tag: buscachefsm HREADY0
+                   else if (HREADY & BusWrite)                        NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm HREADY1
                    else if (HREADY & CacheBusRW[1])                   NextState = CACHE_FETCH;
                    else                                               NextState = ADR_PHASE;
-        DATA_PHASE:  if(HREADY & BusAtomic)                           NextState = ATOMIC_READ_DATA_PHASE;
-                     else if(HREADY & ~BusAtomic)                     NextState = MEM3;
+        DATA_PHASE:  if(HREADY & BusAtomic)                           NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm HREADY2
+                     else if(HREADY & ~BusAtomic)                     NextState = MEM3; // exclusion-tag: buscachefsm HREADY3
                      else                                             NextState = DATA_PHASE;
         ATOMIC_READ_DATA_PHASE: if(HREADY)                            NextState = ATOMIC_PHASE;
                     else                                              NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm Atomic
@@ -105,9 +105,9 @@ module buscachefsm #(
                      else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;
                      else                                             NextState = CACHE_FETCH;
         CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0])  NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback
-                     else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
-                     else if(HREADY & FinalBeatCount & BusCMOZero)    NextState = MEM3;
-                     else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;
+                     else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;     // exclusion-tag: buscachefsm HREADY4
+                     else if(HREADY & FinalBeatCount & BusCMOZero)    NextState = MEM3;            // exclusion-tag: buscachefsm HREADY5
+                     else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;       // exclusion-tag: buscachefsm HREADY6
                      else                                             NextState = CACHE_WRITEBACK;
         default:                                                      NextState = ADR_PHASE;
       endcase
diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S
index e59f26173..216b3c837 100644
--- a/tests/coverage/tlbmisc.S
+++ b/tests/coverage/tlbmisc.S
@@ -101,6 +101,40 @@ main:
     li t1, 10
     amoadd.w t1, t1, (t0)
 
+    la t2, SpecialPage
+    li t0, 0x200000000  # an address to a specific 1 GiB page
+    j ConcurrentICacheMissDTLBMiss
+
+.align 6
+ConcurrentICacheMissDTLBMiss:
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+    lw t1, 0(t0)
+
     # write a cacheline length (512 bits) to memory in uncached region
     li t0, 0x80401000
     cbo.zero (t0)
@@ -303,6 +337,12 @@ pagetable:
     .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 pointing to 0x80150000
     .8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
     .8byte 0x00000000000000C1 # gigapage at VA 0xC0000000 causes access fault
+    .8byte 0x0
+    .8byte 0x0
+    .8byte 0x0
+    .8byte 0x0
+SpecialPage:    
+    .8byte 0x00000000200000CF   # 0x2_0000_0000 1GiB page1
  
 
 # Next page table at 0x80012000 for gigapage at 0x80000000