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make QmM size b+1 indpenedent of radix

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David Harris 2022-09-20 03:25:09 -07:00
parent e455f41b97
commit 87cde2c427
6 changed files with 10 additions and 10 deletions
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2
pipelined/src/fpu/divshiftcalc.sv
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@ -1,7 +1,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module divshiftcalc( module divshiftcalc(
input logic [`DIVb-(`RADIX/4):0] DivQm, input logic [`DIVb:0] DivQm,
input logic [`FMTBITS-1:0] Fmt, input logic [`FMTBITS-1:0] Fmt,
input logic Sqrt, input logic Sqrt,
input logic [`NE+1:0] DivQe, input logic [`NE+1:0] DivQe,

2
pipelined/src/fpu/fdivsqrt.sv
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@ -48,7 +48,7 @@ module fdivsqrt(
output logic DivBusy, output logic DivBusy,
output logic DivDone, output logic DivDone,
output logic [`NE+1:0] QeM, output logic [`NE+1:0] QeM,
output logic [`DIVb-(`RADIX/4):0] QmM output logic [`DIVb:0] QmM
// output logic [`XLEN-1:0] RemM, // output logic [`XLEN-1:0] RemM,
); );

10
pipelined/src/fpu/fdivsqrtpostproc.sv
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@ -37,7 +37,7 @@ module fdivsqrtpostproc(
input logic [`DIVb+1:0] FirstC, input logic [`DIVb+1:0] FirstC,
input logic Firstqn, input logic Firstqn,
input logic SqrtM, input logic SqrtM,
output logic [`DIVb-(`RADIX/4):0] QmM, // *** why output logic [`DIVb:0] QmM,
output logic WZero, output logic WZero,
output logic DivSM output logic DivSM
); );
@ -72,10 +72,10 @@ module fdivsqrtpostproc(
// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
always_comb always_comb
if (SqrtM) begin if (SqrtM) begin
if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << 1; if(NegSticky) QmM = FirstUM[`DIVb:0] << 1;
else QmM = FirstU[`DIVb-(`RADIX/4):0] << 1; else QmM = FirstU[`DIVb:0] << 1;
end else begin // divide end else begin // divide
if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0]; if(NegSticky) QmM = FirstUM[`DIVb:0];
else QmM = FirstU[`DIVb-(`RADIX/4):0]; else QmM = FirstU[`DIVb:0];
end end
endmodule endmodule

2
pipelined/src/fpu/fpu.sv
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@ -123,7 +123,7 @@ module fpu (
logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder) logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder)
//divide signals //divide signals
logic [`DIVb-(`RADIX/4):0] QmM; logic [`DIVb:0] QmM;
logic [`NE+1:0] QeE, QeM; logic [`NE+1:0] QeE, QeM;
logic DivSE, DivSM; logic DivSE, DivSM;
logic DivDoneM; logic DivDoneM;

2
pipelined/src/fpu/postprocess.sv
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@ -59,7 +59,7 @@ module postprocess (
input logic DivS, input logic DivS,
input logic DivDone, input logic DivDone,
input logic [`NE+1:0] DivQe, input logic [`NE+1:0] DivQe,
input logic [`DIVb-(`RADIX/4):0] DivQm, input logic [`DIVb:0] DivQm,
// conversion signals // conversion signals
input logic CvtCs, // the result's sign input logic CvtCs, // the result's sign
input logic [`NE:0] CvtCe, // the calculated expoent input logic [`NE:0] CvtCe, // the calculated expoent

2
pipelined/testbench/testbench-fp.sv
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@ -80,7 +80,7 @@ module testbenchfp;
logic CvtResSgnE; logic CvtResSgnE;
logic [`NE:0] CvtCalcExpE; // the calculated expoent logic [`NE:0] CvtCalcExpE; // the calculated expoent
logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
logic [`DIVb-(`RADIX/4):0] Quot; logic [`DIVb:0] Quot;
logic CvtResDenormUfE; logic CvtResDenormUfE;
logic DivStart, DivBusy; logic DivStart, DivBusy;
logic reset = 1'b0; logic reset = 1'b0;