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Merge pull request #956 from stineje/main

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fix some missing hard-coded paths #647
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David Harris 2024-09-18 13:53:48 -07:00 committed by GitHub
commit 87334e717f
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4 changed files with 5 additions and 10 deletions
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2
bin/fparchtest.sh
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@ -13,8 +13,6 @@
# pip3 install git+https://github.com/riscv/riscv-isac.git
# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg
RISCVCTG=/home/harris/repos/riscv-ctg
#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32
#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32
riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug

2
fpga/generator/wave_config.wcfg
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@ -3,7 +3,7 @@
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/ross/repos/active/cvw/fpga/generator/WallyFPGA.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
<db_ref>
<top_modules>
</top_modules>
</db_ref>

7
linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~
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@ -1,7 +0,0 @@
FPGA_AXI_SDC_MODULE_VERSION = 1.0
FPGA_AXI_SDC_SITE = /home/jpease/repos/fpga-axi-sdc
FPGA_AXI_SDC_SITE_METHOD = local
FPGA_AXI_SDC_LICENSE = GPLv2
$(eval $(kernel-module))
$(eval $(generic-package))

4
site-setup.sh
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@ -30,6 +30,10 @@ export SYN_MW=/home/jstine/MW
export SYN_memory=/home/jstine/WallyMem/rv64gc/
#export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/
# Environmental variables for CTG (https://github.com/riscv-software-src/riscv-ctg)
export RISCVCTG=/home/harris/repos/riscv-ctg
# GCC
if [ -z "$LD_LIBRARY_PATH" ]; then
export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib