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	FPGA makefile update.
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				| @ -3,9 +3,9 @@ sdc_src := ~/repos/sdc.tar.gz | |||||||
| 
 | 
 | ||||||
| # Select the desired board and the all build rules
 | # Select the desired board and the all build rules
 | ||||||
| # vcu118
 | # vcu118
 | ||||||
| #export XILINX_PART := xcvu9p-flga2104-2L-e
 | export XILINX_PART := xcvu9p-flga2104-2L-e | ||||||
| #export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
 | export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 | ||||||
| #export board := vcu118
 | export board := vcu118 | ||||||
| 
 | 
 | ||||||
| # vcu108
 | # vcu108
 | ||||||
| #export XILINX_PART := xcvu095-ffva2104-2-e
 | #export XILINX_PART := xcvu095-ffva2104-2-e
 | ||||||
| @ -13,15 +13,15 @@ sdc_src := ~/repos/sdc.tar.gz | |||||||
| #export board := vcu108
 | #export board := vcu108
 | ||||||
| 
 | 
 | ||||||
| # Arty A7
 | # Arty A7
 | ||||||
| export XILINX_PART := xc7a100tcsg324-1 | #export XILINX_PART := xc7a100tcsg324-1
 | ||||||
| export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1 | #export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
 | ||||||
| export board := ArtyA7 | #export board := ArtyA7
 | ||||||
| 
 | 
 | ||||||
| # for Arty A7 and S7 boards
 | # for Arty A7 and S7 boards
 | ||||||
| all: FPGA_Arty | #all: FPGA_Arty
 | ||||||
| 
 | 
 | ||||||
| # VCU 108 and VCU 118 boards
 | # VCU 108 and VCU 118 boards
 | ||||||
| #all: FPGA_VCU
 | all: FPGA_VCU | ||||||
| 
 | 
 | ||||||
| FPGA_Arty: PreProcessFiles IP_Arty SDC | FPGA_Arty: PreProcessFiles IP_Arty SDC | ||||||
| 	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log | 	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log | ||||||
|  | |||||||
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