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cleanup of ram.sv

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This commit is contained in:
Ross Thompson 2022-03-11 18:09:22 -06:00
parent d43e868e5f
commit 86cc758354
2 changed files with 3 additions and 8 deletions
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3
pipelined/src/lsu/lsu.sv
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@ -106,7 +106,7 @@ module lsu (
logic [`XLEN-1:0] LSUWriteDataM; logic [`XLEN-1:0] LSUWriteDataM;
logic [(`XLEN-1)/8:0] ByteMaskM; logic [(`XLEN-1)/8:0] ByteMaskM;
// *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, // *** TO DO: Burst mode
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
assign IEUAdrExtM = {2'b00, IEUAdrM}; assign IEUAdrExtM = {2'b00, IEUAdrM};
@ -187,7 +187,6 @@ module lsu (
logic SelUncachedAdr; logic SelUncachedAdr;
assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM; assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM;
// *** change to allow TIM and BUS. seaparate parameter for having bus (but have to have bus if have cache - check in testbench)
if (`DMEM == `MEM_TIM) begin : dtim if (`DMEM == `MEM_TIM) begin : dtim
// *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW. // *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW.
// Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops

8
pipelined/src/uncore/ram.sv
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@ -48,7 +48,6 @@ module ram #(parameter BASE=0, RANGE = 65535) (
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)]; logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
logic [31:0] HWADDR, A; logic [31:0] HWADDR, A;
logic [`XLEN-1:0] HREADRam0;
logic prevHREADYRam, risingHREADYRam; logic prevHREADYRam, risingHREADYRam;
logic initTrans; logic initTrans;
@ -157,7 +156,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
HWADDR <= #1 A; HWADDR <= #1 A;
if (`XLEN == 64) begin:ramrw if (`XLEN == 64) begin:ramrw
always_ff @(posedge HCLK) always_ff @(posedge HCLK)
HREADRam0 <= #1 RAM[A[31:3]]; HREADRam <= #1 RAM[A[31:3]];
for(index = 0; index < `XLEN/8; index++) begin for(index = 0; index < `XLEN/8; index++) begin
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:3]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index]; if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:3]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index];
@ -165,7 +164,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
end end
end else begin end else begin
always_ff @(posedge HCLK) always_ff @(posedge HCLK)
HREADRam0 <= #1 RAM[A[31:2]]; HREADRam <= #1 RAM[A[31:2]];
for(index = 0; index < `XLEN/8; index++) begin for(index = 0; index < `XLEN/8; index++) begin
always_ff @(posedge HCLK) begin:ramrw always_ff @(posedge HCLK) begin:ramrw
if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:2]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index]; if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:2]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index];
@ -174,8 +173,5 @@ module ram #(parameter BASE=0, RANGE = 65535) (
end end
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
//assign HREADRam = HREADYRam ? HREADRam0 : `XLEN'bz;
// *** Ross Thompson: removed tristate as fpga synthesis removes.
assign HREADRam = HREADRam0;
endmodule endmodule