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https://github.com/openhwgroup/cvw
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cclsm cleanup.
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@ -79,6 +79,7 @@ module align import cvw::*; #(parameter cvw_t P) (
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logic [$clog2(LLENINBYTES)-1:0] ByteOffsetM;
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logic [$clog2(LLENINBYTES)-1:0] ByteOffsetM;
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logic HalfSpillM, WordSpillM;
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logic HalfSpillM, WordSpillM;
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logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM;
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logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM;
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logic [$clog2(LLENINBYTES)+2:0] ShiftAmount;
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logic ValidAccess;
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logic ValidAccess;
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/* verilator lint_off WIDTHEXPAND */
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/* verilator lint_off WIDTHEXPAND */
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@ -167,14 +168,15 @@ module align import cvw::*; #(parameter cvw_t P) (
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// shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
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// shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
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// 8 * is for shifting by bytes not bits
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// 8 * is for shifting by bytes not bits
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assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> (ValidMisalignedM ? 8 * AccessByteOffsetM : '0);
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assign ShiftAmount = ValidMisalignedM ? 8 * AccessByteOffsetM : '0;
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assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount;
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assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
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assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
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// write path. Also has the 8:1 shifter muxing for the byteoffset
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// write path. Also has the 8:1 shifter muxing for the byteoffset
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// then it also has the mux to select when a spill occurs
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// then it also has the mux to select when a spill occurs
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logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM; // *** RT: Find a better way. I've extending in both directions so we don't shift in zeros. The cache expects the writedata to not have any zero data, but instead replicated data.
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logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM; // *** RT: Find a better way. I've extending in both directions so we don't shift in zeros. The cache expects the writedata to not have any zero data, but instead replicated data.
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assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << (ValidMisalignedM ? 8 * AccessByteOffsetM : '0);
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assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount;
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assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
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assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
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mux3 #(2*P.LLEN/8) bytemaskspillmux(ByteMaskMuxM, // no spill
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mux3 #(2*P.LLEN/8) bytemaskspillmux(ByteMaskMuxM, // no spill
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