Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Renamed Word to Beat for ahbcacheinterface.

Browse Source
This commit is contained in:
Ross Thompson 2022-11-09 17:52:50 -06:00
parent 028e2b0f91
commit 8658a25218
5 changed files with 62 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
pipelined/src/cache/cache.sv vendored
View File

@ -54,8 +54,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// Bus fsm interface // Bus fsm interface
output logic [1:0] CacheBusRW, output logic [1:0] CacheBusRW,
input logic CacheBusAck, input logic CacheBusAck,
input logic SelBusWord, input logic SelBusBeat,
input logic [LOGBWPL-1:0] WordCount, input logic [LOGBWPL-1:0] BeatCount,
input logic [LINELEN-1:0] FetchBuffer, input logic [LINELEN-1:0] FetchBuffer,
output logic [`PA_BITS-1:0] CacheBusAdr, output logic [`PA_BITS-1:0] CacheBusAdr,
output logic [WORDLEN-1:0] ReadDataWord); output logic [WORDLEN-1:0] ReadDataWord);
@ -143,7 +143,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// like to fix this. // like to fix this.
if(DCACHE) if(DCACHE)
mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]),
.d1(WordCount), .s(SelBusWord), .d1(BeatCount), .s(SelBusBeat),
.y(WordOffsetAddr)); .y(WordOffsetAddr));
else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];

26
pipelined/src/ebu/ahbcacheinterface.sv
View File

@ -34,7 +34,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
( (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
@ -46,7 +46,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
output logic [1:0] HTRANS, output logic [1:0] HTRANS,
output logic HWRITE, output logic HWRITE,
output logic [`PA_BITS-1:0] HADDR, output logic [`PA_BITS-1:0] HADDR,
output logic [LOGWPL-1:0] WordCount, output logic [LOGWPL-1:0] BeatCount,
// cache interface // cache interface
input logic [`PA_BITS-1:0] CacheBusAdr, input logic [`PA_BITS-1:0] CacheBusAdr,
@ -61,30 +61,30 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
input logic [1:0] BusRW, input logic [1:0] BusRW,
input logic CPUBusy, input logic CPUBusy,
input logic [2:0] Funct3, input logic [2:0] Funct3,
output logic SelBusWord, output logic SelBusBeat,
output logic BusStall, output logic BusStall,
output logic BusCommitted); output logic BusCommitted);
localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0;
logic [`PA_BITS-1:0] LocalHADDR; logic [`PA_BITS-1:0] LocalHADDR;
logic [LOGWPL-1:0] WordCountDelayed; logic [LOGWPL-1:0] BeatCountDelayed;
logic CaptureEn; logic CaptureEn;
genvar index; genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
logic [WORDSPERLINE-1:0] CaptureWord; logic [BEATSPERLINE-1:0] CaptureBeat;
assign CaptureWord[index] = CaptureEn & (index == WordCountDelayed); assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureWord[index]), .d(HRDATA), flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
.q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
end end
mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR); mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`XLEN/8)) + LocalHADDR;
mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE)); mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
.HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
.CacheBusRW, .CacheBusAck, .WordCount, .WordCountDelayed, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST); .HREADY, .HTRANS, .HWRITE, .HBURST);
endmodule endmodule

68
pipelined/src/ebu/buscachefsm.sv
View File

@ -32,7 +32,7 @@
`define BURST_EN 1 `define BURST_EN 1
// HCLK and clk must be the same clock! // HCLK and clk must be the same clock!
module buscachefsm #(parameter integer WordCountThreshold, module buscachefsm #(parameter integer BeatCountThreshold,
parameter integer LOGWPL, parameter logic CACHE_ENABLED ) parameter integer LOGWPL, parameter logic CACHE_ENABLED )
(input logic HCLK, (input logic HCLK,
input logic HRESETn, input logic HRESETn,
@ -50,8 +50,8 @@ module buscachefsm #(parameter integer WordCountThreshold,
output logic CacheBusAck, output logic CacheBusAck,
// lsu interface // lsu interface
output logic [LOGWPL-1:0] WordCount, WordCountDelayed, output logic [LOGWPL-1:0] BeatCount, BeatCountDelayed,
output logic SelBusWord, output logic SelBusBeat,
// BUS interface // BUS interface
input logic HREADY, input logic HREADY,
@ -70,11 +70,11 @@ module buscachefsm #(parameter integer WordCountThreshold,
(* mark_debug = "true" *) busstatetype CurrState, NextState; (* mark_debug = "true" *) busstatetype CurrState, NextState;
logic [LOGWPL-1:0] NextWordCount; logic [LOGWPL-1:0] NextBeatCount;
logic FinalWordCount; logic FinalBeatCount;
logic [2:0] LocalBurstType; logic [2:0] LocalBurstType;
logic WordCntEn; logic BeatCntEn;
logic WordCntReset; logic BeatCntReset;
logic CacheAccess; logic CacheAccess;
always_ff @(posedge HCLK) always_ff @(posedge HCLK)
@ -91,13 +91,13 @@ module buscachefsm #(parameter integer WordCountThreshold,
else NextState = DATA_PHASE; else NextState = DATA_PHASE;
MEM3: if(CPUBusy) NextState = MEM3; MEM3: if(CPUBusy) NextState = MEM3;
else NextState = ADR_PHASE; else NextState = ADR_PHASE;
CACHE_FETCH: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE; else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE;
else NextState = CACHE_FETCH; else NextState = CACHE_FETCH;
CACHE_WRITEBACK: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE; else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE;
else NextState = CACHE_WRITEBACK; else NextState = CACHE_WRITEBACK;
default: NextState = ADR_PHASE; default: NextState = ADR_PHASE;
endcase endcase
@ -105,25 +105,25 @@ module buscachefsm #(parameter integer WordCountThreshold,
// IEU, LSU, and IFU controls // IEU, LSU, and IFU controls
flopenr #(LOGWPL) flopenr #(LOGWPL)
WordCountReg(.clk(HCLK), BeatCountReg(.clk(HCLK),
.reset(~HRESETn | WordCntReset), .reset(~HRESETn | BeatCntReset),
.en(WordCntEn), .en(BeatCntEn),
.d(NextWordCount), .d(NextBeatCount),
.q(WordCount)); .q(BeatCount));
// Used to store data from data phase of AHB. // Used to store data from data phase of AHB.
flopenr #(LOGWPL) flopenr #(LOGWPL)
WordCountDelayedReg(.clk(HCLK), BeatCountDelayedReg(.clk(HCLK),
.reset(~HRESETn | WordCntReset), .reset(~HRESETn | BeatCntReset),
.en(WordCntEn), .en(BeatCntEn),
.d(WordCount), .d(BeatCount),
.q(WordCountDelayed)); .q(BeatCountDelayed));
assign NextWordCount = WordCount + 1'b1; assign NextBeatCount = BeatCount + 1'b1;
assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0]; assign FinalBeatCount = BeatCountDelayed == BeatCountThreshold[LOGWPL-1:0];
assign WordCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) | assign BeatCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) |
(NextState == ADR_PHASE & |CacheBusRW & HREADY); (NextState == ADR_PHASE & |CacheBusRW & HREADY);
assign WordCntReset = NextState == ADR_PHASE; assign BeatCntReset = NextState == ADR_PHASE;
assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY); assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY);
assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
@ -137,14 +137,14 @@ module buscachefsm #(parameter integer WordCountThreshold,
// AHB bus interface // AHB bus interface
assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) | assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) |
(CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request
(CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |WordCount); assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |BeatCount);
assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |WordCount)) ? LocalBurstType : 3'b0; assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;
always_comb begin always_comb begin
case(WordCountThreshold) case(BeatCountThreshold)
0: LocalBurstType = 3'b000; 0: LocalBurstType = 3'b000;
3: LocalBurstType = 3'b011; // INCR4 3: LocalBurstType = 3'b011; // INCR4
7: LocalBurstType = 3'b101; // INCR8 7: LocalBurstType = 3'b101; // INCR8
@ -154,8 +154,8 @@ module buscachefsm #(parameter integer WordCountThreshold,
end end
// communication to cache // communication to cache
assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount); assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount);
assign SelBusWord = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) | assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) |
(CurrState == DATA_PHASE & BusRW[0]) | (CurrState == DATA_PHASE & BusRW[0]) |
(CurrState == CACHE_WRITEBACK) | (CurrState == CACHE_WRITEBACK) |
(CurrState == CACHE_FETCH); (CurrState == CACHE_FETCH);

5
pipelined/src/ifu/ifu.sv
View File

@ -205,6 +205,7 @@ module ifu (
assign IFURWF = 2'b10; assign IFURWF = 2'b10;
end end
if (`BUS) begin : bus if (`BUS) begin : bus
// **** must fix words per line vs beats per line as in lsu.
localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
if(`ICACHE) begin : icache if(`ICACHE) begin : icache
@ -227,7 +228,7 @@ module ifu (
.ReadDataWord(ICacheInstrF), .ReadDataWord(ICacheInstrF),
.SelHPTW('0), .SelHPTW('0),
.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
.ByteMask('0), .WordCount('0), .SelBusWord('0), .ByteMask('0), .BeatCount('0), .SelBusBeat('0),
.FinalWriteData('0), .FinalWriteData('0),
.CacheRW(CacheRWF), .CacheRW(CacheRWF),
.CacheAtomic('0), .FlushCache('0), .CacheAtomic('0), .FlushCache('0),
@ -239,7 +240,7 @@ module ifu (
.HRDATA, .HRDATA,
.Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
.WordCount(), .Cacheable(CacheableF), .SelBusWord(), .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(),
.CacheBusAck(ICacheBusAck), .CacheBusAck(ICacheBusAck),
.FetchBuffer, .PAdr(PCPF), .FetchBuffer, .PAdr(PCPF),
.BusRW, .CPUBusy, .BusRW, .CPUBusy,

18
pipelined/src/lsu/lsu.sv
View File

@ -222,17 +222,17 @@ module lsu (
if (`BUS) begin : bus if (`BUS) begin : bus
localparam integer LLENWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`LLEN : 1; localparam integer LLENWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`LLEN : 1;
localparam integer LLENLOGBWPL = `DCACHE ? $clog2(LLENWORDSPERLINE) : 1; localparam integer LLENLOGBWPL = `DCACHE ? $clog2(LLENWORDSPERLINE) : 1;
localparam integer AHBWWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1; localparam integer BEATSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1;
localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(AHBWWORDSPERLINE) : 1; localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(BEATSPERLINE) : 1;
if(`DCACHE) begin : dcache if(`DCACHE) begin : dcache
localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN; localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
logic [LINELEN-1:0] FetchBuffer; logic [LINELEN-1:0] FetchBuffer;
logic [`PA_BITS-1:0] DCacheBusAdr; logic [`PA_BITS-1:0] DCacheBusAdr;
logic DCacheWriteLine; logic DCacheWriteLine;
logic DCacheFetchLine; logic DCacheFetchLine;
logic [AHBWLOGBWPL-1:0] WordCount; logic [AHBWLOGBWPL-1:0] BeatCount;
logic DCacheBusAck; logic DCacheBusAck;
logic SelBusWord; logic SelBusBeat;
logic [`XLEN-1:0] PreHWDATA; //*** change name logic [`XLEN-1:0] PreHWDATA; //*** change name
logic [`XLEN/8-1:0] ByteMaskMDelay; logic [`XLEN/8-1:0] ByteMaskMDelay;
logic [1:0] CacheBusRW, BusRW; logic [1:0] CacheBusRW, BusRW;
@ -249,20 +249,20 @@ module lsu (
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
.clk, .reset, .CPUBusy, .SelBusWord, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .clk, .reset, .CPUBusy, .SelBusBeat, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
.FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
.ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
.FinalWriteData(LSUWriteDataM), .SelHPTW, .FinalWriteData(LSUWriteDataM), .SelHPTW,
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.CacheCommitted(DCacheCommittedM), .CacheCommitted(DCacheCommittedM),
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM),
.FetchBuffer, .CacheBusRW, .FetchBuffer, .CacheBusRW,
.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
ahbcacheinterface #(.WORDSPERLINE(AHBWWORDSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface(
.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
.HRDATA, .HRDATA,
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
.WordCount, .SelBusWord, .BeatCount, .SelBusBeat,
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW,
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
.Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy, .Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy,
@ -284,7 +284,7 @@ module lsu (
for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
assign AHBWordSets[index] = DCacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; assign AHBWordSets[index] = DCacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)];
end end
assign DCacheReadDataWordAHB = AHBWordSets[WordCount[$clog2(LLENPOVERAHBW)-1:0]]; assign DCacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0]; end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0];
mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]), mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]),
.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));