diff --git a/wally-pipelined/src/sdc/sd_clk_fsm.sv b/wally-pipelined/src/sdc/sd_clk_fsm.sv index dfbc4e396..094bac7ad 100644 --- a/wally-pipelined/src/sdc/sd_clk_fsm.sv +++ b/wally-pipelined/src/sdc/sd_clk_fsm.sv @@ -36,14 +36,14 @@ module sd_clk_fsm ( - input logic CLK, - input logic i_RST, - output logic o_DONE, - input logic i_START, - input logic i_FATAL_ERROR, - output logic o_HS_TO_INIT_CLK_DIVIDER_RST, // resets clock divider that is going from 50 MHz to 400 KHz - output logic o_SD_CLK_SELECTED, // which clock is selected ('0'=HS or '1'=init) - output logic o_G_CLK_SD_EN); // Turns gated clock (G_CLK_SD) off and on + input logic CLK, + input logic i_RST, + (* mark_debug = "true" *)output logic o_DONE, + (* mark_debug = "true" *)input logic i_START, + (* mark_debug = "true" *)input logic i_FATAL_ERROR, + (* mark_debug = "true" *)output logic o_HS_TO_INIT_CLK_DIVIDER_RST, // resets clock divider that is going from 50 MHz to 400 KHz + (* mark_debug = "true" *)output logic o_SD_CLK_SELECTED, // which clock is selected ('0'=HS or '1'=init) + (* mark_debug = "true" *)output logic o_G_CLK_SD_EN); // Turns gated clock (G_CLK_SD) off and on logic [3:0] w_next_state; diff --git a/wally-pipelined/src/sdc/sd_dat_fsm.sv b/wally-pipelined/src/sdc/sd_dat_fsm.sv index 7168391f7..acf0098c3 100644 --- a/wally-pipelined/src/sdc/sd_dat_fsm.sv +++ b/wally-pipelined/src/sdc/sd_dat_fsm.sv @@ -33,41 +33,41 @@ module sd_dat_fsm input logic i_RST, // Timer module control input logic i_SD_CLK_SELECTED, // Which frequency I'm in determines what count in to load for a 100ms timer - output logic o_TIMER_LOAD, o_TIMER_EN, // Timer Control signals - output logic [22:0] o_TIMER_IN, // Need Enough bits for 100 milliseconds at 48MHz - input logic [22:0] i_TIMER_OUT, // (ceiling(log((clk freq)(delay desired)-1)/log(2))-1) downto 0 + (* mark_debug = "true" *)output logic o_TIMER_LOAD, o_TIMER_EN, // Timer Control signals + (* mark_debug = "true" *)output logic [22:0] o_TIMER_IN, // Need Enough bits for 100 milliseconds at 48MHz + (* mark_debug = "true" *)input logic [22:0] i_TIMER_OUT, // (ceiling(log((clk freq)(delay desired)-1)/log(2))-1) downto 0 // Nibble counter module control - output logic o_COUNTER_RST, o_COUNTER_EN, // nibble counter - input logic [10:0] i_COUNTER_OUT, // max nibbles is 1024 + crc16 bits = 1040 bits + (* mark_debug = "true" *)output logic o_COUNTER_RST, o_COUNTER_EN, // nibble counter + (* mark_debug = "true" *)input logic [10:0] i_COUNTER_OUT, // max nibbles is 1024 + crc16 bits = 1040 bits // CRC16 Generation control - output logic o_CRC16_EN, o_CRC16_RST, // shared signals for all 4 CRC16_SIPO (one for each of 4 DAT lines) - input logic i_DATA_CRC16_GOOD, // indicates that no errors in transmission when CRC16 are all zero + (* mark_debug = "true" *)output logic o_CRC16_EN, o_CRC16_RST, // shared signals for all 4 CRC16_SIPO (one for each of 4 DAT lines) + (* mark_debug = "true" *)input logic i_DATA_CRC16_GOOD, // indicates that no errors in transmission when CRC16 are all zero // For R1b - output logic o_BUSY_RST, o_BUSY_EN, // busy signal for R1b - input logic i_DAT0_Q, + (* mark_debug = "true" *)output logic o_BUSY_RST, o_BUSY_EN, // busy signal for R1b + (* mark_debug = "true" *)input logic i_DAT0_Q, // Storage Buffers for DAT bits read - output logic o_NIBO_EN, // 512 bytes block data (Nibble In Block Out) + (* mark_debug = "true" *)output logic o_NIBO_EN, // 512 bytes block data (Nibble In Block Out) // From LUT - input logic [1:0] i_USES_DAT, // current command needs use of DAT bus + (* mark_debug = "true" *)input logic [1:0] i_USES_DAT, // current command needs use of DAT bus // For communicating with core - output logic o_DATA_VALID, // indicates that DATA being send over o_DATA to core is valid - output logic o_LAST_NIBBLE, // indicates that the last nibble has been sent + (* mark_debug = "true" *)output logic o_DATA_VALID, // indicates that DATA being send over o_DATA to core is valid + (* mark_debug = "true" *)output logic o_LAST_NIBBLE, // indicates that the last nibble has been sent // For communication with sd_cmd_fsm - input logic i_CMD_TX_DONE, // command transmission completed, begin waiting for DATA - output logic o_DAT_RX_DONE, // tell SD_CMD_FSM that DAT communication is completed, send next instruction to sd card - output logic o_ERROR_DAT_TIMES_OUT, // error flag for when DAT times out (so don't fetch more instructions) - output logic o_DAT_ERROR_FD_RST, - output logic o_DAT_ERROR_FD_EN, // tell SD_CMD_FSM to resend command due to error in transmission + (* mark_debug = "true" *)input logic i_CMD_TX_DONE, // command transmission completed, begin waiting for DATA + (* mark_debug = "true" *)output logic o_DAT_RX_DONE, // tell SD_CMD_FSM that DAT communication is completed, send next instruction to sd card + (* mark_debug = "true" *)output logic o_ERROR_DAT_TIMES_OUT, // error flag for when DAT times out (so don't fetch more instructions) + (* mark_debug = "true" *)output logic o_DAT_ERROR_FD_RST, + (* mark_debug = "true" *)output logic o_DAT_ERROR_FD_EN, // tell SD_CMD_FSM to resend command due to error in transmission input logic LIMIT_SD_TIMERS ); (* mark_debug = "true" *) logic [3:0] w_next_state, r_curr_state; - logic w_error_crc16_fd_en, w_error_crc16_fd_rst, w_error_crc16_fd_d; // Save ERROR_CRC16 so CMD FSM sees it in IDLE_NRC (not just in IDLE_DAT) + (* mark_debug = "true" *) logic w_error_crc16_fd_en, w_error_crc16_fd_rst, w_error_crc16_fd_d; // Save ERROR_CRC16 so CMD FSM sees it in IDLE_NRC (not just in IDLE_DAT) logic r_error_crc16_fd_Q; - logic [22:0] Identify_Timer_In; - logic [22:0] Data_TX_Timer_In; + (* mark_debug = "true" *) logic [22:0] Identify_Timer_In; + (* mark_debug = "true" *) logic [22:0] Data_TX_Timer_In; localparam logic [3:0] s_reset = 4'b0000; localparam logic [3:0] s_idle = 4'b0001; diff --git a/wally-pipelined/src/sdc/sd_top.sv b/wally-pipelined/src/sdc/sd_top.sv index a796f2143..1e789256b 100644 --- a/wally-pipelined/src/sdc/sd_top.sv +++ b/wally-pipelined/src/sdc/sd_top.sv @@ -156,16 +156,16 @@ module sd_top #(parameter g_COUNT_WIDTH = 8) localparam logic [127:96] c_ACMD55_ans_error_free = 32'h00000000; // SD_CMD_FSM Connections - logic w_TIMER_LOAD, w_TIMER_EN; - logic [18:0] w_TIMER_IN; - logic [18:0] r_TIMER_OUT; - logic w_COUNTER_LOAD, w_COUNTER_EN; - logic [7:0] w_COUNTER_IN; - logic [7:0] r_COUNTER_OUT; - logic w_SD_CLK_EN; - logic w_CLOCK_CHANGE_DONE, w_START_CLOCK_CHANGE; // to clk fsm - logic w_HS_TO_INIT_CLK_DIVIDER_RST; - logic w_IC_RST, w_IC_EN, w_IC_UP_DOWN; + (* mark_debug = "true" *)logic w_TIMER_LOAD, w_TIMER_EN; + (* mark_debug = "true" *)logic [18:0] w_TIMER_IN; + (* mark_debug = "true" *)logic [18:0] r_TIMER_OUT; + (* mark_debug = "true" *)logic w_COUNTER_LOAD, w_COUNTER_EN; + (* mark_debug = "true" *)logic [7:0] w_COUNTER_IN; + (* mark_debug = "true" *)logic [7:0] r_COUNTER_OUT; + (* mark_debug = "true" *)logic w_SD_CLK_EN; + (* mark_debug = "true" *)logic w_CLOCK_CHANGE_DONE, w_START_CLOCK_CHANGE; // to clk fsm + (* mark_debug = "true" *)logic w_HS_TO_INIT_CLK_DIVIDER_RST; + (* mark_debug = "true" *)logic w_IC_RST, w_IC_EN, w_IC_UP_DOWN; //logic w_USES_DAT : std_logic_vector(1 downto 0); //logic w_OPCODE_Q : std_logic_vector(6 downto 0); //logic w_R_TYPE : std_logic_vector(2 downto 0); @@ -173,88 +173,88 @@ module sd_top #(parameter g_COUNT_WIDTH = 8) //logic w_NO_REDO_ANS : std_logic_vector(31 downto 0); //logic w_NO_ERROR_MASK : std_logic_vector(31 downto 0); //logic w_NO_ERROR_ANS : std_logic_vector(31 downto 0); - logic w_SD_CMD_OE; + (* mark_debug = "true" *)logic w_SD_CMD_OE; //logic w_SD_CMD_IE : std_logic; // tri-state buffer - input enable (for simulation only) - logic w_TX_PISO40_LOAD, w_TX_PISO40_EN; - logic w_TX_PISO8_LOAD, w_TX_PISO8_EN; - logic w_TX_CRC7_PIPO_RST, w_TX_CRC7_PIPO_EN; - logic [1:0] w_TX_SOURCE_SELECT; - logic w_CMD_TX_IS_CMD55_RST; - logic w_CMD_TX_IS_CMD55_EN; + (* mark_debug = "true" *)logic w_TX_PISO40_LOAD, w_TX_PISO40_EN; + (* mark_debug = "true" *)logic w_TX_PISO8_LOAD, w_TX_PISO8_EN; + (* mark_debug = "true" *)logic w_TX_CRC7_PIPO_RST, w_TX_CRC7_PIPO_EN; + (* mark_debug = "true" *)logic [1:0] w_TX_SOURCE_SELECT; + (* mark_debug = "true" *)logic w_CMD_TX_IS_CMD55_RST; + (* mark_debug = "true" *)logic w_CMD_TX_IS_CMD55_EN; //logic w_CMD_RX; - logic w_RX_SIPO48_RST, w_RX_SIPO48_EN; - logic [39:8] r_RESPONSE_CONTENT; - logic [45:40] r_RESPONSE_INDEX; - logic w_RX_CRC7_SIPO_RST, w_RX_CRC7_SIPO_EN; - logic [6:0] r_RX_CRC7_Q; - logic w_RCA_REGISTER_RST, w_RCA_REGISTER_EN; - logic w_CMD_TX_DONE; - logic w_DAT_RX_DONE; - logic w_DAT_ERROR_FD_RST_DAT, w_DAT_ERROR_FD_RST_CMD, w_DAT_ERROR_FD_RST, w_DAT_ERROR_FD_EN; - logic r_DAT_ERROR_Q; // CRC16 error or time out - logic w_NOT_DAT_ERROR_Q; // '0'=no error, '1'=tx error on DAT bus - logic w_ERROR_DAT_TIMES_OUT; - logic w_FATAL_ERROR; - logic [2:0] r_ERROR_CODE_Q; // indicates which fatal error occured + (* mark_debug = "true" *)logic w_RX_SIPO48_RST, w_RX_SIPO48_EN; + (* mark_debug = "true" *)logic [39:8] r_RESPONSE_CONTENT; + (* mark_debug = "true" *)logic [45:40] r_RESPONSE_INDEX; + (* mark_debug = "true" *)logic w_RX_CRC7_SIPO_RST, w_RX_CRC7_SIPO_EN; + (* mark_debug = "true" *)logic [6:0] r_RX_CRC7_Q; + (* mark_debug = "true" *)logic w_RCA_REGISTER_RST, w_RCA_REGISTER_EN; + (* mark_debug = "true" *)logic w_CMD_TX_DONE; + (* mark_debug = "true" *)logic w_DAT_RX_DONE; + (* mark_debug = "true" *)logic w_DAT_ERROR_FD_RST_DAT, w_DAT_ERROR_FD_RST_CMD, w_DAT_ERROR_FD_RST, w_DAT_ERROR_FD_EN; + (* mark_debug = "true" *)logic r_DAT_ERROR_Q; // CRC16 error or time out + (* mark_debug = "true" *)logic w_NOT_DAT_ERROR_Q; // '0'=no error, '1'=tx error on DAT bus + (* mark_debug = "true" *)logic w_ERROR_DAT_TIMES_OUT; + (* mark_debug = "true" *)logic w_FATAL_ERROR; + (* mark_debug = "true" *)logic [2:0] r_ERROR_CODE_Q; // indicates which fatal error occured // Communication with core - logic w_READY_FOR_READ; - logic w_READ_REQUEST; - logic [3:0] r_DATA_TO_CORE; - logic w_DATA_VALID; - logic w_LAST_NIBBLE; + (* mark_debug = "true" *)logic w_READY_FOR_READ; + (* mark_debug = "true" *)logic w_READ_REQUEST; + (* mark_debug = "true" *)logic [3:0] r_DATA_TO_CORE; + (* mark_debug = "true" *)logic w_DATA_VALID; + (* mark_debug = "true" *)logic w_LAST_NIBBLE; //SD_DAT_FSM Connections - logic w_DAT_TIMER_LOAD, w_DAT_TIMER_EN; - logic w_DAT_COUNTER_RST, w_DAT_COUNTER_EN; - logic w_CRC16_EN, w_CRC16_RST; - logic w_BUSY_RST, w_BUSY_EN; - logic w_NIBO_EN; - logic w_DATA_CRC16_GOOD; - logic w_VALID_BLOCK_D, w_VALID_BLOCK_EN, w_VALID_WIDE_D, w_VALID_WIDE_EN; - logic [22:0] w_DAT_TIMER_IN; - logic [22:0] r_DAT_TIMER_OUT; - logic [10:0] r_DAT_COUNTER_OUT; - logic [3:0] r_DAT_Q; + (* mark_debug = "true" *)logic w_DAT_TIMER_LOAD, w_DAT_TIMER_EN; + (* mark_debug = "true" *)logic w_DAT_COUNTER_RST, w_DAT_COUNTER_EN; + (* mark_debug = "true" *)logic w_CRC16_EN, w_CRC16_RST; + (* mark_debug = "true" *)logic w_BUSY_RST, w_BUSY_EN; + (* mark_debug = "true" *)logic w_NIBO_EN; + (* mark_debug = "true" *)logic w_DATA_CRC16_GOOD; + (* mark_debug = "true" *)logic w_VALID_BLOCK_D, w_VALID_BLOCK_EN, w_VALID_WIDE_D, w_VALID_WIDE_EN; + (* mark_debug = "true" *)logic [22:0] w_DAT_TIMER_IN; + (* mark_debug = "true" *)logic [22:0] r_DAT_TIMER_OUT; + (* mark_debug = "true" *)logic [10:0] r_DAT_COUNTER_OUT; + (* mark_debug = "true" *)logic [3:0] r_DAT_Q; // RCA Register - logic [15:0] w_RCA_D_Q; - logic [15:0] r_RCA_Q2; + (* mark_debug = "true" *)logic [15:0] w_RCA_D_Q; + (* mark_debug = "true" *)logic [15:0] r_RCA_Q2; // Multiplexer Logics (* mark_debug = "true" *) logic [132:0] w_instruction_control_bits; - logic [132:130] w_R_TYPE ; - logic [129:128] w_USES_DAT ; - logic [127:96] w_NO_REDO_MASK ; - logic [95:64] w_NO_REDO_ANS ; - logic [63:32] w_NO_ERROR_MASK ; - logic [31:0] w_NO_ERROR_ANS ; - logic [45:40] w_command_index ; - logic [39:8] w_command_arguments ; - logic [47:8] w_command_head ; - logic [6:0] w_OPCODE_Q ; + (* mark_debug = "true" *)logic [132:130] w_R_TYPE ; + (* mark_debug = "true" *)logic [129:128] w_USES_DAT ; + (* mark_debug = "true" *)logic [127:96] w_NO_REDO_MASK ; + (* mark_debug = "true" *)logic [95:64] w_NO_REDO_ANS ; + (* mark_debug = "true" *)logic [63:32] w_NO_ERROR_MASK ; + (* mark_debug = "true" *)logic [31:0] w_NO_ERROR_ANS ; + (* mark_debug = "true" *)logic [45:40] w_command_index ; + (* mark_debug = "true" *)logic [39:8] w_command_arguments ; + (* mark_debug = "true" *)logic [47:8] w_command_head ; + (* mark_debug = "true" *)logic [6:0] w_OPCODE_Q ; // TOP_LEVEL Connections - logic [40:9] w_BLOCK_ADDR ; - logic [3:0] r_IC_OUT ; - logic [2:0] r_command_index_is_55_history ; // [0] is live index, [1] is currently saved index, [2] is index of previous command - logic r_previous_command_index_was_55_q; // is index of previous command 55, wired to r_command_index_is_55_history[2] - logic r_ACMD_Q; // if the previous command sent to the SD card successfully had index 55, then the SD card thinks the current command is ACMD - logic [4095:0] r_block_data ; // data block from CMD17 + (* mark_debug = "true" *)logic [40:9] w_BLOCK_ADDR ; + (* mark_debug = "true" *)logic [3:0] r_IC_OUT ; + (* mark_debug = "true" *)logic [2:0] r_command_index_is_55_history ; // [0] is live index, [1] is currently saved index, [2] is index of previous command + (* mark_debug = "true" *)logic r_previous_command_index_was_55_q; // is index of previous command 55, wired to r_command_index_is_55_history[2] + (* mark_debug = "true" *)logic r_ACMD_Q; // if the previous command sent to the SD card successfully had index 55, then the SD card thinks the current command is ACMD + (* mark_debug = "true" *)logic [4095:0] r_block_data ; // data block from CMD17 // TX - logic [45:8] w_command_content; // first 40 bits of command packet - logic w_tx_head_Q; // transmission of first part of command packet - logic w_tx_tail_Q; // transmission of last part of command packet - logic [7:0] r_command_tail; // last 8 bits of command packet - logic [6:0] r_TX_CRC7; + (* mark_debug = "true" *)logic [45:8] w_command_content; // first 40 bits of command packet + (* mark_debug = "true" *)logic w_tx_head_Q; // transmission of first part of command packet + (* mark_debug = "true" *)logic w_tx_tail_Q; // transmission of last part of command packet + (* mark_debug = "true" *)logic [7:0] r_command_tail; // last 8 bits of command packet + (* mark_debug = "true" *)logic [6:0] r_TX_CRC7; //logic w_TX_Q:= '0'; // actual transmission when tx is enabled // RX - logic [47:0] r_RX_RESPONSE; + (* mark_debug = "true" *)logic [47:0] r_RX_RESPONSE; // Tri state IO Driver BC18MIMS - logic w_SD_CMD_TX_Q; // Write Data + (* mark_debug = "true" *)logic w_SD_CMD_TX_Q; // Write Data (* mark_debug = "true" *) logic w_SD_CMD_RX; // Read Data @@ -263,17 +263,17 @@ module sd_top #(parameter g_COUNT_WIDTH = 8) //logic r_SD_CLK_ungated := '0'; // Selected clock before it is clock gated //logic r_SD_CLK := '0'; // GATED CLOCKS - logic r_TO_SD_CLK; // What is actually sent to the SD card + (* mark_debug = "true" *)logic r_TO_SD_CLK; // What is actually sent to the SD card - logic w_G_CLK_SD_EN; - logic r_CLK_SD, r_G_CLK_SD; // clocks - logic r_G_CLK_SD_n; - logic [15:0] r_CLK_FSM_RST ; // a_rst logic delayed by one 1.2 GHz period - logic w_SD_CLK_SELECTED; + (* mark_debug = "true" *)logic w_G_CLK_SD_EN; + (* mark_debug = "true" *)logic r_CLK_SD, r_G_CLK_SD; // clocks + (* mark_debug = "true" *)logic r_G_CLK_SD_n; + (* mark_debug = "true" *)logic [15:0] r_CLK_FSM_RST ; // a_rst logic delayed by one 1.2 GHz period + (* mark_debug = "true" *)logic w_SD_CLK_SELECTED; //DAT FSM Connections - logic [15:0] r_DAT3_CRC16, r_DAT2_CRC16, r_DAT1_CRC16; - logic [15:0] r_DAT0_CRC16; + (* mark_debug = "true" *)logic [15:0] r_DAT3_CRC16, r_DAT2_CRC16, r_DAT1_CRC16; + (* mark_debug = "true" *)logic [15:0] r_DAT0_CRC16; assign w_BLOCK_ADDR = {8'h00, i_BLOCK_ADDR}; // (40 downto 36 are zero since card is 64 GB) @@ -491,7 +491,8 @@ module sd_top #(parameter g_COUNT_WIDTH = 8) // Clock selection clkdivider #(g_COUNT_WIDTH) slow_clk_divider // Divide 50 MHz to <400 KHz (Initial clock) (.i_COUNT_IN_MAX(i_COUNT_IN_MAX), - .i_EN(w_SD_CLK_SELECTED), + //.i_EN(w_SD_CLK_SELECTED), + .i_EN(1'b1), .i_RST(w_HS_TO_INIT_CLK_DIVIDER_RST), .i_CLK(CLK), .o_CLK(r_CLK_SD)); diff --git a/wally-pipelined/testbench/common/sdModel.sv b/wally-pipelined/testbench/common/sdModel.sv index 52795dd05..9450282e7 100644 --- a/wally-pipelined/testbench/common/sdModel.sv +++ b/wally-pipelined/testbench/common/sdModel.sv @@ -145,6 +145,71 @@ module sdModel //initial $readmemh(SD_FILE, FLASHmem); initial begin + wide_data[0] <= 'h00; + wide_data[1] <= 'hc8; + wide_data[2] <= 'h80; + wide_data[3] <= 'h01; + wide_data[4] <= 'h80; + wide_data[5] <= 'h01; + wide_data[6] <= 'h80; + wide_data[7] <= 'h01; + wide_data[8] <= 'h80; + wide_data[9] <= 'h01; + wide_data[10] <= 'hc0; + wide_data[11] <= 'h01; + wide_data[12] <= 'h80; + wide_data[13] <= 'h03; + wide_data[14] <= 'h00; + wide_data[15] <= 'h00; + wide_data[16] <= 'h01; + wide_data[17] <= 00; + wide_data[18] <= 00; + wide_data[19] <= 00; + wide_data[20] <= 00; + wide_data[21] <= 00; + wide_data[22] <= 00; + wide_data[23] <= 00; + wide_data[24] <= 00; + wide_data[25] <= 00; + wide_data[26] <= 00; + wide_data[27] <= 00; + wide_data[28] <= 00; + wide_data[29] <= 00; + wide_data[30] <= 00; + wide_data[31] <= 00; + wide_data[32] <= 00; + wide_data[33] <= 00; + wide_data[34] <= 00; + wide_data[35] <= 00; + wide_data[36] <= 00; + wide_data[37] <= 00; + wide_data[38] <= 00; + wide_data[39] <= 00; + wide_data[40] <= 00; + wide_data[41] <= 00; + wide_data[42] <= 00; + wide_data[43] <= 00; + wide_data[44] <= 00; + wide_data[45] <= 00; + wide_data[46] <= 00; + wide_data[47] <= 00; + wide_data[48] <= 00; + wide_data[49] <= 00; + wide_data[50] <= 00; + wide_data[51] <= 00; + wide_data[52] <= 00; + wide_data[53] <= 00; + wide_data[54] <= 00; + wide_data[55] <= 00; + wide_data[56] <= 00; + wide_data[57] <= 00; + wide_data[58] <= 00; + wide_data[59] <= 00; + wide_data[60] <= 00; + wide_data[61] <= 00; + wide_data[62] <= 00; + wide_data[63] <= 00; +/* -----\/----- EXCLUDED -----\/----- wide_data[0] <= 00; wide_data[1] <= 20; wide_data[2] <= 80; @@ -209,6 +274,7 @@ module sdModel wide_data[61] <= 00; wide_data[62] <= 00; wide_data[63] <= 00; + -----/\----- EXCLUDED -----/\----- */ end