diff --git a/pipelined/src/fpu/divshiftcalc.sv b/pipelined/src/fpu/divshiftcalc.sv
index 1c2305fb5..8c66f8098 100644
--- a/pipelined/src/fpu/divshiftcalc.sv
+++ b/pipelined/src/fpu/divshiftcalc.sv
@@ -1,7 +1,7 @@
 `include "wally-config.vh"
 
 module divshiftcalc(
-    input logic  [`DIVb-(`RADIX/4):0] DivQm,
+    input logic  [`DIVb:0] DivQm,
     input logic  [`FMTBITS-1:0] Fmt,
     input logic Sqrt,
     input logic [`NE+1:0] DivQe,
diff --git a/pipelined/src/fpu/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv
index 2671e19f5..ba6a4ef78 100644
--- a/pipelined/src/fpu/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt.sv
@@ -48,7 +48,7 @@ module fdivsqrt(
   output logic DivBusy,
   output logic DivDone,
   output logic [`NE+1:0] QeM,
-  output logic [`DIVb-(`RADIX/4):0] QmM
+  output logic [`DIVb:0] QmM
 //   output logic [`XLEN-1:0] RemM,
 );
 
diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv
index 75f8795ef..e1e6a5ec0 100644
--- a/pipelined/src/fpu/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrtpostproc.sv
@@ -37,7 +37,7 @@ module fdivsqrtpostproc(
   input logic [`DIVb+1:0] FirstC,
   input logic  Firstqn,
   input logic SqrtM,
-  output logic [`DIVb-(`RADIX/4):0] QmM, // *** why
+  output logic [`DIVb:0] QmM, 
   output logic WZero,
   output logic DivSM
 );
@@ -72,10 +72,10 @@ module fdivsqrtpostproc(
    // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
   always_comb
     if (SqrtM) begin
-      if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << 1;
-      else          QmM = FirstU[`DIVb-(`RADIX/4):0]  << 1;
+      if(NegSticky) QmM = FirstUM[`DIVb:0] << 1;
+      else          QmM = FirstU[`DIVb:0]  << 1;
     end else begin // divide
-      if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0];
-      else          QmM = FirstU[`DIVb-(`RADIX/4):0];
+      if(NegSticky) QmM = FirstUM[`DIVb:0];
+      else          QmM = FirstU[`DIVb:0];
     end
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv
index 48598d560..84109b610 100755
--- a/pipelined/src/fpu/fpu.sv
+++ b/pipelined/src/fpu/fpu.sv
@@ -123,7 +123,7 @@ module fpu (
    logic [`CVTLEN-1:0]     CvtLzcInE, CvtLzcInM;      // input to the Leading Zero Counter (priority encoder)
    
    //divide signals
-   logic [`DIVb-(`RADIX/4):0] QmM;
+   logic [`DIVb:0]      QmM;
    logic [`NE+1:0]      QeE, QeM; 
    logic                DivSE, DivSM;
    logic                DivDoneM;
diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv
index 761ae04de..145eac129 100644
--- a/pipelined/src/fpu/postprocess.sv
+++ b/pipelined/src/fpu/postprocess.sv
@@ -59,7 +59,7 @@ module postprocess (
     input logic                             DivS,
     input logic                             DivDone,
     input logic  [`NE+1:0]                  DivQe,
-    input logic  [`DIVb-(`RADIX/4):0]                DivQm,
+    input logic  [`DIVb:0]                  DivQm,
     // conversion signals
     input logic                             CvtCs,     // the result's sign
     input logic  [`NE:0]                    CvtCe,    // the calculated expoent
diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv
index 06f810a32..9f7df893b 100644
--- a/pipelined/testbench/testbench-fp.sv
+++ b/pipelined/testbench/testbench-fp.sv
@@ -80,7 +80,7 @@ module testbenchfp;
   logic CvtResSgnE;
   logic [`NE:0]           CvtCalcExpE;    // the calculated expoent
 	logic [`LOGCVTLEN-1:0] CvtShiftAmtE;  // how much to shift by
-	logic [`DIVb-(`RADIX/4):0] Quot;
+	logic [`DIVb:0] Quot;
   logic CvtResDenormUfE;
   logic DivStart, DivBusy;
   logic reset = 1'b0;