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Finished removing generate statements

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This commit is contained in:
David Harris 2022-01-05 16:41:17 +00:00
parent 32590d484c
commit 85fa620cfb
9 changed files with 151 additions and 220 deletions
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3
pipelined/src/fpu/fcmp.sv
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@ -71,14 +71,13 @@ module fcmp (
// - return 0 if comparison with NaN (unordered) // - return 0 if comparison with NaN (unordered)
logic [`FLEN-1:0] QNaNX, QNaNY; logic [`FLEN-1:0] QNaNX, QNaNY;
generate if(`IEEE754) begin if(`IEEE754) begin
assign QNaNX = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]}; assign QNaNX = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]};
assign QNaNY = FmtE ? {YSgnE, YExpE, 1'b1, YManE[`NF-2:0]} : {{32{1'b1}}, YSgnE, YExpE[7:0], 1'b1, YManE[50:29]}; assign QNaNY = FmtE ? {YSgnE, YExpE, 1'b1, YManE[`NF-2:0]} : {{32{1'b1}}, YSgnE, YExpE[7:0], 1'b1, YManE[50:29]};
end else begin end else begin
assign QNaNX = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0}; assign QNaNX = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0};
assign QNaNY = FmtE ? {1'b0, YExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpE[7:0], 1'b1, 22'b0}; assign QNaNY = FmtE ? {1'b0, YExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpE[7:0], 1'b1, 22'b0};
end end
endgenerate
always_comb begin always_comb begin
case (FOpCtrlE[2:0]) case (FOpCtrlE[2:0])

26
pipelined/src/uncore/sdc/SDC.sv
View File

@ -156,17 +156,15 @@ module SDC
flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (CommandCompleted), flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (CommandCompleted),
CommandCompleted ? '0 : HWDATA[2:0], '0, Command); CommandCompleted ? '0 : HWDATA[2:0], '0, Command);
generate if (`XLEN == 64) begin
if (`XLEN == 64) begin flopenr #(64-9) AddressReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite),
flopenr #(64-9) AddressReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite), HWDATA[`XLEN-1:9], Address);
HWDATA[`XLEN-1:9], Address); end else begin
end else begin flopenr #(32-9) AddressLowReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite),
flopenr #(32-9) AddressLowReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite), HWDATA[`XLEN-1:9], Address[31:9]);
HWDATA[`XLEN-1:9], Address[31:9]); flopenr #(32) AddressHighReg(HCLK, ~HRESETn, (HADDRDelay == 'h14 & RegWrite),
flopenr #(32) AddressHighReg(HCLK, ~HRESETn, (HADDRDelay == 'h14 & RegWrite), HWDATA, Address[63:32]);
HWDATA, Address[63:32]); end
end
endgenerate
flopen #(`XLEN) DataReg(HCLK, (HADDRDelay == 'h18 & RegWrite), flopen #(`XLEN) DataReg(HCLK, (HADDRDelay == 'h18 & RegWrite),
HWDATA, SDCWriteData); HWDATA, SDCWriteData);
@ -175,7 +173,6 @@ module SDC
assign Status = {ErrorCode, InvalidCommand, SDCBusy, SDCInitialized}; assign Status = {ErrorCode, InvalidCommand, SDCBusy, SDCInitialized};
generate
if(`XLEN == 64) begin if(`XLEN == 64) begin
always_comb always_comb
case(HADDRDelay[4:0]) case(HADDRDelay[4:0])
@ -200,7 +197,6 @@ module SDC
default: HREADSDC = {24'b0, CLKDiv}; default: HREADSDC = {24'b0, CLKDiv};
endcase endcase
end end
endgenerate
for(index = 0; index < 4096/`XLEN; index++) begin for(index = 0; index < 4096/`XLEN; index++) begin
@ -208,8 +204,7 @@ module SDC
end end
assign SDCReadDataPreNibbleSwap = ReadData512ByteWords[WordCount]; assign SDCReadDataPreNibbleSwap = ReadData512ByteWords[WordCount];
generate if(`XLEN == 64) begin
if(`XLEN == 64) begin
assign SDCReadData = {SDCReadDataPreNibbleSwap[59:56], SDCReadDataPreNibbleSwap[63:60], assign SDCReadData = {SDCReadDataPreNibbleSwap[59:56], SDCReadDataPreNibbleSwap[63:60],
SDCReadDataPreNibbleSwap[51:48], SDCReadDataPreNibbleSwap[55:52], SDCReadDataPreNibbleSwap[51:48], SDCReadDataPreNibbleSwap[55:52],
SDCReadDataPreNibbleSwap[43:40], SDCReadDataPreNibbleSwap[47:44], SDCReadDataPreNibbleSwap[43:40], SDCReadDataPreNibbleSwap[47:44],
@ -224,7 +219,6 @@ module SDC
SDCReadDataPreNibbleSwap[11:8], SDCReadDataPreNibbleSwap[15:12], SDCReadDataPreNibbleSwap[11:8], SDCReadDataPreNibbleSwap[15:12],
SDCReadDataPreNibbleSwap[3:0], SDCReadDataPreNibbleSwap[7:4]}; SDCReadDataPreNibbleSwap[3:0], SDCReadDataPreNibbleSwap[7:4]};
end end
endgenerate
flopenr #($clog2(4096/`XLEN)) WordCountReg flopenr #($clog2(4096/`XLEN)) WordCountReg
(.clk(HCLK), (.clk(HCLK),

15
pipelined/src/uncore/sdc/clkdivider.sv
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@ -88,17 +88,6 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
assign w_fd_D = ~ r_fd_Q; assign w_fd_D = ~ r_fd_Q;
if(`FPGA) BUFGMUX clkMux(.I1(r_fd_Q), .I0(i_CLK), .S(i_EN), .O(o_CLK));
generate else assign o_CLK = i_EN ? r_fd_Q : i_CLK;
if(`FPGA) begin
BUFGMUX
clkMux(.I1(r_fd_Q),
.I0(i_CLK),
.S(i_EN),
.O(o_CLK));
end else begin
assign o_CLK = i_EN ? r_fd_Q : i_CLK;
end
endgenerate
endmodule endmodule

49
pipelined/src/uncore/uartPC16550D.sv
View File

@ -257,12 +257,9 @@ module uartPC16550D(
else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right
end end
generate // ***explain why
if(`QEMU) if(`QEMU) assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10); // implies rxstate = UART_ACTIVE
assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10); // implies rxstate = UART_ACTIVE else assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE
else
assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE
endgenerate
assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit
@ -325,22 +322,20 @@ module uartPC16550D(
// detect any errors in rx fifo // detect any errors in rx fifo
// although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop // although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop
// tail is normally higher than head, but might wrap around. unwrapped variable adds 16 to eliminate wrapping // tail is normally higher than head, but might wrap around. unwrapped variable adds 16 to eliminate wrapping
generate assign rxfifotailunwrapped = rxfifotail < rxfifohead ? {1'b1, rxfifotail} : {1'b0, rxfifotail};
assign rxfifotailunwrapped = rxfifotail < rxfifohead ? {1'b1, rxfifotail} : {1'b0, rxfifotail}; genvar i;
genvar i; for (i=0; i<32; i++) begin:rxfull
for (i=0; i<32; i++) begin:rxfull if (i == 0) assign rxfullbitunwrapped[i] = (rxfifohead==0) & (rxfifotail != 0);
if (i == 0) assign rxfullbitunwrapped[i] = (rxfifohead==0) & (rxfifotail != 0); else assign rxfullbitunwrapped[i] = ({1'b0,rxfifohead}==i | rxfullbitunwrapped[i-1]) & (rxfifotailunwrapped != i);
else assign rxfullbitunwrapped[i] = ({1'b0,rxfifohead}==i | rxfullbitunwrapped[i-1]) & (rxfifotailunwrapped != i); end
end for (i=0; i<16; i++) begin:rx
for (i=0; i<16; i++) begin:rx assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set? assign rxfullbit[i] = rxfullbitunwrapped[i] | rxfullbitunwrapped[i+16];
assign rxfullbit[i] = rxfullbitunwrapped[i] | rxfullbitunwrapped[i+16]; /* if (i > 0)
/* if (i > 0) assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);
assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i); else
else assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/ end
end
endgenerate
assign rxfifohaserr = |(RXerrbit & rxfullbit); assign rxfifohaserr = |(RXerrbit & rxfullbit);
// receive buffer register and ready bit // receive buffer register and ready bit
@ -383,13 +378,9 @@ module uartPC16550D(
end end
assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s) assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s)
generate // *** explain; is this necessary?
if (`QEMU) if (`QEMU) assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00); // implies txstate = UART_ACTIVE
assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00); // implies txstate = UART_ACTIVE else assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE
else
assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE
endgenerate
/////////////////////////////////////////// ///////////////////////////////////////////
// transmit holding register, shift register, FIFO // transmit holding register, shift register, FIFO

162
pipelined/src/wally/wallypipelinedhart.sv
View File

@ -304,88 +304,84 @@ module wallypipelinedhart (
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW .FlushF, .FlushD, .FlushE, .FlushM, .FlushW
); // global stall and flush control ); // global stall and flush control
generate if (`ZICSR_SUPPORTED) begin:priv
if (`ZICSR_SUPPORTED) begin:priv privileged priv(
privileged priv( .clk, .reset,
.clk, .reset, .FlushD, .FlushE, .FlushM, .FlushW,
.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
.StallD, .StallE, .StallM, .StallW, .CSRReadM, .CSRWriteM, .SrcAM, .PCM,
.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .InstrM, .CSRReadValW, .PrivilegedNextPCM,
.InstrM, .CSRReadValW, .PrivilegedNextPCM, .RetM, .TrapM,
.RetM, .TrapM, .ITLBFlushF, .DTLBFlushM,
.ITLBFlushF, .DTLBFlushM, .InstrValidM, .CommittedM,
.InstrValidM, .CommittedM, .FRegWriteM, .LoadStallD,
.FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM, .ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
.LoadMisalignedFaultM, .StoreMisalignedFaultM, .TimerIntM, .ExtIntM, .SwIntM,
.TimerIntM, .ExtIntM, .SwIntM, .MTIME_CLINT,
.MTIME_CLINT, .InstrMisalignedAdrM, .IEUAdrM,
.InstrMisalignedAdrM, .IEUAdrM, .SetFflagsM,
.SetFflagsM, // Trap signals from pmp/pma in mmu
// Trap signals from pmp/pma in mmu // *** do these need to be split up into one for dmem and one for ifu?
// *** do these need to be split up into one for dmem and one for ifu? // instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem? .InstrAccessFaultF, .LoadAccessFaultM, .StoreAccessFaultM,
.InstrAccessFaultF, .LoadAccessFaultM, .StoreAccessFaultM, .ExceptionM, .PendingInterruptM, .IllegalFPUInstrE,
.ExceptionM, .PendingInterruptM, .IllegalFPUInstrE, .PrivilegeModeW, .SATP_REGW,
.PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .FRM_REGW,.BreakpointFaultM, .EcallFaultM
.FRM_REGW,.BreakpointFaultM, .EcallFaultM );
); end else begin
end else begin assign CSRReadValW = 0;
assign CSRReadValW = 0; assign PrivilegedNextPCM = 0;
assign PrivilegedNextPCM = 0; assign RetM = 0;
assign RetM = 0; assign TrapM = 0;
assign TrapM = 0; assign ITLBFlushF = 0;
assign ITLBFlushF = 0; assign DTLBFlushM = 0;
assign DTLBFlushM = 0; end
end if (`M_SUPPORTED) begin:mdu
if (`M_SUPPORTED) begin:mdu muldiv mdu(
muldiv mdu( .clk, .reset,
.clk, .reset, .ForwardedSrcAE, .ForwardedSrcBE,
.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MulDivE, .W64E,
.Funct3E, .Funct3M, .MulDivE, .W64E, .MulDivResultW, .DivBusyE,
.MulDivResultW, .DivBusyE, .StallM, .StallW, .FlushM, .FlushW
.StallM, .StallW, .FlushM, .FlushW );
); end else begin // no M instructions supported
end else begin // no M instructions supported assign MulDivResultW = 0;
assign MulDivResultW = 0; assign DivBusyE = 0;
assign DivBusyE = 0; end
end
if (`F_SUPPORTED) begin:fpu if (`F_SUPPORTED) begin:fpu
fpu fpu( fpu fpu(
.clk, .reset, .clk, .reset,
.FRM_REGW, // Rounding mode from CSR .FRM_REGW, // Rounding mode from CSR
.InstrD, // instruction from IFU .InstrD, // instruction from IFU
.ReadDataW,// Read data from memory .ReadDataW,// Read data from memory
.ForwardedSrcAE, // Integer input being processed (from IEU) .ForwardedSrcAE, // Integer input being processed (from IEU)
.StallE, .StallM, .StallW, // stall signals from HZU .StallE, .StallM, .StallW, // stall signals from HZU
.FlushE, .FlushM, .FlushW, // flush signals from HZU .FlushE, .FlushM, .FlushW, // flush signals from HZU
.RdM, .RdW, // which FP register to write to (from IEU) .RdM, .RdW, // which FP register to write to (from IEU)
.FRegWriteM, // FP register write enable .FRegWriteM, // FP register write enable
.FStallD, // Stall the decode stage .FStallD, // Stall the decode stage
.FWriteIntE, // integer register write enable .FWriteIntE, // integer register write enable
.FWriteDataE, // Data to be written to memory .FWriteDataE, // Data to be written to memory
.FIntResM, // data to be written to integer register .FIntResM, // data to be written to integer register
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
.IllegalFPUInstrD, // Is the instruction an illegal fpu instruction .IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
.SetFflagsM // FPU flags (to privileged unit) .SetFflagsM // FPU flags (to privileged unit)
); // floating point unit ); // floating point unit
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
assign FStallD = 0; assign FStallD = 0;
assign FWriteIntE = 0; assign FWriteIntE = 0;
assign FWriteDataE = 0; assign FWriteDataE = 0;
assign FIntResM = 0; assign FIntResM = 0;
assign FDivBusyE = 0; assign FDivBusyE = 0;
assign IllegalFPUInstrD = 1; assign IllegalFPUInstrD = 1;
assign SetFflagsM = 0; assign SetFflagsM = 0;
end end
endgenerate
// Priveleged block operates in M and W stages, handling CSRs and exceptions
endmodule endmodule

8
pipelined/testbench/common/sdModel.sv
View File

@ -121,11 +121,9 @@ module sdModel
integer sdModel_file_desc; integer sdModel_file_desc;
genvar i; genvar i;
generate for(i=0; i<4; i=i+1) begin:CRC_16_gen
for(i=0; i<4; i=i+1) begin:CRC_16_gen sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);
sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]); end
end
endgenerate
sd_crc_7 crc_7 sd_crc_7 crc_7
( (

54
pipelined/testbench/testbench-fpga.sv
View File

@ -763,17 +763,12 @@ string tests32f[] = '{
.done(DCacheFlushDone)); .done(DCacheFlushDone));
generate // initialize the branch predictor
// initialize the branch predictor if (`BPRED_ENABLED == 1)
if (`BPRED_ENABLED == 1) begin : bpred initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
initial begin $readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
$readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
end
end end
endgenerate
endmodule endmodule
module riscvassertions(); module riscvassertions();
@ -830,29 +825,26 @@ module DCacheFlushFSM
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)]; logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
generate for(index = 0; index < numlines; index++) begin
for(index = 0; index < numlines; index++) begin for(way = 0; way < numways; way++) begin
for(way = 0; way < numways; way++) begin for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin copyShadow #(.tagstart(tagstart), .loglinebytelen(loglinebytelen))
copyShadow #(.tagstart(tagstart), copyShadow(.clk,
.loglinebytelen(loglinebytelen)) .start,
copyShadow(.clk, .tag(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
.start, .valid(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].ValidBits[index]),
.tag(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]), .dirty(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
.valid(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].ValidBits[index]), .data(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
.dirty(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].DirtyBits[index]), .index(index),
.data(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]), .cacheWord(cacheWord),
.index(index), .CacheData(CacheData[way][index][cacheWord]),
.cacheWord(cacheWord), .CacheAdr(CacheAdr[way][index][cacheWord]),
.CacheData(CacheData[way][index][cacheWord]), .CacheTag(CacheTag[way][index][cacheWord]),
.CacheAdr(CacheAdr[way][index][cacheWord]), .CacheValid(CacheValid[way][index][cacheWord]),
.CacheTag(CacheTag[way][index][cacheWord]), .CacheDirty(CacheDirty[way][index][cacheWord]));
.CacheValid(CacheValid[way][index][cacheWord]),
.CacheDirty(CacheDirty[way][index][cacheWord]));
end
end end
end end
endgenerate end
integer i, j, k; integer i, j, k;

9
pipelined/testbench/testbench-linux.sv
View File

@ -22,7 +22,7 @@
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// When letting Wally go for it, let wally generate own interrupts // When letting Wally go for it, let wally make own interrupts
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
@ -280,13 +280,6 @@ module testbench;
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1); `INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3); `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3);
generate
genvar i;
/* -----\/----- EXCLUDED -----\/-----
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPCFG, [7:0],`PMP_ENTRIES-1,0);
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPADDR, [`XLEN-1:0],`PMP_ENTRIES-1,0);
-----/\----- EXCLUDED -----/\----- */
endgenerate
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);

37
pipelined/testbench/testbench.sv
View File

@ -296,13 +296,8 @@ logic [3:0] dummy;
// or sw gp, -56(t0) // or sw gp, -56(t0)
// or on a jump to self infinite loop (6f) for RISC-V Arch tests // or on a jump to self infinite loop (6f) for RISC-V Arch tests
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
generate if (`ZICSR_SUPPORTED) assign ecf = dut.hart.priv.priv.EcallFaultM;
if (`ZICSR_SUPPORTED) begin else assign ecf = 0;
assign ecf = dut.hart.priv.priv.EcallFaultM;
end else begin
assign ecf = 0;
end
endgenerate
assign DCacheFlushStart = ecf & assign DCacheFlushStart = ecf &
(dut.hart.ieu.dp.regf.rf[3] == 1 | (dut.hart.ieu.dp.regf.rf[3] == 1 |
(dut.hart.ieu.dp.regf.we3 & (dut.hart.ieu.dp.regf.we3 &
@ -310,24 +305,17 @@ logic [3:0] dummy;
dut.hart.ieu.dp.regf.wd3 == 1)) | dut.hart.ieu.dp.regf.wd3 == 1)) |
(dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM; (dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
// **** Fix when the check in the shadow ram is fixed.
DCacheFlushFSM DCacheFlushFSM(.clk(clk), DCacheFlushFSM DCacheFlushFSM(.clk(clk),
.reset(reset), .reset(reset),
.start(DCacheFlushStart), .start(DCacheFlushStart),
.done(DCacheFlushDone)); .done(DCacheFlushDone));
// initialize the branch predictor
generate if (`BPRED_ENABLED == 1)
// initialize the branch predictor initial begin
if (`BPRED_ENABLED == 1) begin : bpred $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
end
end end
endgenerate
endmodule endmodule
module riscvassertions; module riscvassertions;
@ -370,7 +358,6 @@ module DCacheFlushFSM
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)]; logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
generate
if(`MEM_DCACHE) begin if(`MEM_DCACHE) begin
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES; localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS; localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
@ -430,15 +417,7 @@ module DCacheFlushFSM
end end
endgenerate flop #(1) doneReg(.clk, .d(start), .q(done));
flop #(1) doneReg(.clk(clk),
.d(start),
.q(done));
endmodule endmodule
module copyShadow module copyShadow