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https://github.com/openhwgroup/cvw
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Finished removing generate statements
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@ -71,14 +71,13 @@ module fcmp (
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// - return 0 if comparison with NaN (unordered)
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// - return 0 if comparison with NaN (unordered)
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logic [`FLEN-1:0] QNaNX, QNaNY;
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logic [`FLEN-1:0] QNaNX, QNaNY;
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generate if(`IEEE754) begin
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if(`IEEE754) begin
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assign QNaNX = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]};
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assign QNaNX = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]};
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assign QNaNY = FmtE ? {YSgnE, YExpE, 1'b1, YManE[`NF-2:0]} : {{32{1'b1}}, YSgnE, YExpE[7:0], 1'b1, YManE[50:29]};
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assign QNaNY = FmtE ? {YSgnE, YExpE, 1'b1, YManE[`NF-2:0]} : {{32{1'b1}}, YSgnE, YExpE[7:0], 1'b1, YManE[50:29]};
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end else begin
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end else begin
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assign QNaNX = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0};
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assign QNaNX = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0};
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assign QNaNY = FmtE ? {1'b0, YExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpE[7:0], 1'b1, 22'b0};
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assign QNaNY = FmtE ? {1'b0, YExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpE[7:0], 1'b1, 22'b0};
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end
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end
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endgenerate
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always_comb begin
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always_comb begin
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case (FOpCtrlE[2:0])
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case (FOpCtrlE[2:0])
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@ -156,17 +156,15 @@ module SDC
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flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (CommandCompleted),
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flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (CommandCompleted),
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CommandCompleted ? '0 : HWDATA[2:0], '0, Command);
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CommandCompleted ? '0 : HWDATA[2:0], '0, Command);
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generate
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if (`XLEN == 64) begin
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if (`XLEN == 64) begin
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flopenr #(64-9) AddressReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite),
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flopenr #(64-9) AddressReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite),
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HWDATA[`XLEN-1:9], Address);
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HWDATA[`XLEN-1:9], Address);
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end else begin
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end else begin
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flopenr #(32-9) AddressLowReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite),
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flopenr #(32-9) AddressLowReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite),
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HWDATA[`XLEN-1:9], Address[31:9]);
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HWDATA[`XLEN-1:9], Address[31:9]);
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flopenr #(32) AddressHighReg(HCLK, ~HRESETn, (HADDRDelay == 'h14 & RegWrite),
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flopenr #(32) AddressHighReg(HCLK, ~HRESETn, (HADDRDelay == 'h14 & RegWrite),
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HWDATA, Address[63:32]);
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HWDATA, Address[63:32]);
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end
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end
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endgenerate
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flopen #(`XLEN) DataReg(HCLK, (HADDRDelay == 'h18 & RegWrite),
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flopen #(`XLEN) DataReg(HCLK, (HADDRDelay == 'h18 & RegWrite),
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HWDATA, SDCWriteData);
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HWDATA, SDCWriteData);
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@ -175,7 +173,6 @@ module SDC
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assign Status = {ErrorCode, InvalidCommand, SDCBusy, SDCInitialized};
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assign Status = {ErrorCode, InvalidCommand, SDCBusy, SDCInitialized};
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generate
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if(`XLEN == 64) begin
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if(`XLEN == 64) begin
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always_comb
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always_comb
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case(HADDRDelay[4:0])
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case(HADDRDelay[4:0])
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@ -200,7 +197,6 @@ module SDC
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default: HREADSDC = {24'b0, CLKDiv};
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default: HREADSDC = {24'b0, CLKDiv};
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endcase
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endcase
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end
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end
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endgenerate
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for(index = 0; index < 4096/`XLEN; index++) begin
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for(index = 0; index < 4096/`XLEN; index++) begin
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@ -208,8 +204,7 @@ module SDC
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end
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end
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assign SDCReadDataPreNibbleSwap = ReadData512ByteWords[WordCount];
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assign SDCReadDataPreNibbleSwap = ReadData512ByteWords[WordCount];
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generate
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if(`XLEN == 64) begin
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if(`XLEN == 64) begin
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assign SDCReadData = {SDCReadDataPreNibbleSwap[59:56], SDCReadDataPreNibbleSwap[63:60],
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assign SDCReadData = {SDCReadDataPreNibbleSwap[59:56], SDCReadDataPreNibbleSwap[63:60],
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SDCReadDataPreNibbleSwap[51:48], SDCReadDataPreNibbleSwap[55:52],
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SDCReadDataPreNibbleSwap[51:48], SDCReadDataPreNibbleSwap[55:52],
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SDCReadDataPreNibbleSwap[43:40], SDCReadDataPreNibbleSwap[47:44],
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SDCReadDataPreNibbleSwap[43:40], SDCReadDataPreNibbleSwap[47:44],
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@ -224,7 +219,6 @@ module SDC
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SDCReadDataPreNibbleSwap[11:8], SDCReadDataPreNibbleSwap[15:12],
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SDCReadDataPreNibbleSwap[11:8], SDCReadDataPreNibbleSwap[15:12],
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SDCReadDataPreNibbleSwap[3:0], SDCReadDataPreNibbleSwap[7:4]};
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SDCReadDataPreNibbleSwap[3:0], SDCReadDataPreNibbleSwap[7:4]};
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end
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end
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endgenerate
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flopenr #($clog2(4096/`XLEN)) WordCountReg
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flopenr #($clog2(4096/`XLEN)) WordCountReg
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(.clk(HCLK),
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(.clk(HCLK),
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@ -88,17 +88,6 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
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assign w_fd_D = ~ r_fd_Q;
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assign w_fd_D = ~ r_fd_Q;
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if(`FPGA) BUFGMUX clkMux(.I1(r_fd_Q), .I0(i_CLK), .S(i_EN), .O(o_CLK));
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generate
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else assign o_CLK = i_EN ? r_fd_Q : i_CLK;
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if(`FPGA) begin
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BUFGMUX
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clkMux(.I1(r_fd_Q),
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.I0(i_CLK),
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.S(i_EN),
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.O(o_CLK));
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end else begin
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assign o_CLK = i_EN ? r_fd_Q : i_CLK;
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end
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endgenerate
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endmodule
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endmodule
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@ -257,12 +257,9 @@ module uartPC16550D(
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else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right
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else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right
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end
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end
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generate
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// ***explain why
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if(`QEMU)
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if(`QEMU) assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10); // implies rxstate = UART_ACTIVE
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assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10); // implies rxstate = UART_ACTIVE
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else assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE
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else
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assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE
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endgenerate
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assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit
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assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit
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@ -325,22 +322,20 @@ module uartPC16550D(
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// detect any errors in rx fifo
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// detect any errors in rx fifo
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// although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop
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// although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop
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// tail is normally higher than head, but might wrap around. unwrapped variable adds 16 to eliminate wrapping
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// tail is normally higher than head, but might wrap around. unwrapped variable adds 16 to eliminate wrapping
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generate
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assign rxfifotailunwrapped = rxfifotail < rxfifohead ? {1'b1, rxfifotail} : {1'b0, rxfifotail};
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assign rxfifotailunwrapped = rxfifotail < rxfifohead ? {1'b1, rxfifotail} : {1'b0, rxfifotail};
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genvar i;
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genvar i;
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for (i=0; i<32; i++) begin:rxfull
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for (i=0; i<32; i++) begin:rxfull
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if (i == 0) assign rxfullbitunwrapped[i] = (rxfifohead==0) & (rxfifotail != 0);
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if (i == 0) assign rxfullbitunwrapped[i] = (rxfifohead==0) & (rxfifotail != 0);
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else assign rxfullbitunwrapped[i] = ({1'b0,rxfifohead}==i | rxfullbitunwrapped[i-1]) & (rxfifotailunwrapped != i);
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else assign rxfullbitunwrapped[i] = ({1'b0,rxfifohead}==i | rxfullbitunwrapped[i-1]) & (rxfifotailunwrapped != i);
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end
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end
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for (i=0; i<16; i++) begin:rx
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for (i=0; i<16; i++) begin:rx
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assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
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assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
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assign rxfullbit[i] = rxfullbitunwrapped[i] | rxfullbitunwrapped[i+16];
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assign rxfullbit[i] = rxfullbitunwrapped[i] | rxfullbitunwrapped[i+16];
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/* if (i > 0)
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/* if (i > 0)
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assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);
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assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);
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else
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else
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assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
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assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
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end
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end
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endgenerate
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assign rxfifohaserr = |(RXerrbit & rxfullbit);
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assign rxfifohaserr = |(RXerrbit & rxfullbit);
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// receive buffer register and ready bit
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// receive buffer register and ready bit
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@ -383,13 +378,9 @@ module uartPC16550D(
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end
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end
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assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s)
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assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s)
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generate
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// *** explain; is this necessary?
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if (`QEMU)
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if (`QEMU) assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00); // implies txstate = UART_ACTIVE
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assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00); // implies txstate = UART_ACTIVE
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else assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE
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else
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assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE
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endgenerate
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///////////////////////////////////////////
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///////////////////////////////////////////
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// transmit holding register, shift register, FIFO
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// transmit holding register, shift register, FIFO
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@ -304,88 +304,84 @@ module wallypipelinedhart (
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.FlushF, .FlushD, .FlushE, .FlushM, .FlushW
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.FlushF, .FlushD, .FlushE, .FlushM, .FlushW
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); // global stall and flush control
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); // global stall and flush control
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generate
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if (`ZICSR_SUPPORTED) begin:priv
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if (`ZICSR_SUPPORTED) begin:priv
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privileged priv(
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privileged priv(
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.clk, .reset,
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.clk, .reset,
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.FlushD, .FlushE, .FlushM, .FlushW,
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.FlushD, .FlushE, .FlushM, .FlushW,
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.StallD, .StallE, .StallM, .StallW,
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.StallD, .StallE, .StallM, .StallW,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
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.InstrM, .CSRReadValW, .PrivilegedNextPCM,
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.InstrM, .CSRReadValW, .PrivilegedNextPCM,
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.RetM, .TrapM,
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.RetM, .TrapM,
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.ITLBFlushF, .DTLBFlushM,
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.ITLBFlushF, .DTLBFlushM,
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.InstrValidM, .CommittedM,
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.InstrValidM, .CommittedM,
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.FRegWriteM, .LoadStallD,
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.FRegWriteM, .LoadStallD,
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.BPPredDirWrongM, .BTBPredPCWrongM,
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.BPPredDirWrongM, .BTBPredPCWrongM,
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.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
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.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
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.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
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.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
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.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
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.LoadMisalignedFaultM, .StoreMisalignedFaultM,
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.LoadMisalignedFaultM, .StoreMisalignedFaultM,
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.TimerIntM, .ExtIntM, .SwIntM,
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.TimerIntM, .ExtIntM, .SwIntM,
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.MTIME_CLINT,
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.MTIME_CLINT,
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.InstrMisalignedAdrM, .IEUAdrM,
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.InstrMisalignedAdrM, .IEUAdrM,
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.SetFflagsM,
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.SetFflagsM,
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// Trap signals from pmp/pma in mmu
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// Trap signals from pmp/pma in mmu
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// *** do these need to be split up into one for dmem and one for ifu?
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// *** do these need to be split up into one for dmem and one for ifu?
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// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
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// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
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.InstrAccessFaultF, .LoadAccessFaultM, .StoreAccessFaultM,
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.InstrAccessFaultF, .LoadAccessFaultM, .StoreAccessFaultM,
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.ExceptionM, .PendingInterruptM, .IllegalFPUInstrE,
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.ExceptionM, .PendingInterruptM, .IllegalFPUInstrE,
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.PrivilegeModeW, .SATP_REGW,
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.PrivilegeModeW, .SATP_REGW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.FRM_REGW,.BreakpointFaultM, .EcallFaultM
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.FRM_REGW,.BreakpointFaultM, .EcallFaultM
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);
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);
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end else begin
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end else begin
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assign CSRReadValW = 0;
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assign CSRReadValW = 0;
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assign PrivilegedNextPCM = 0;
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assign PrivilegedNextPCM = 0;
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assign RetM = 0;
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assign RetM = 0;
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assign TrapM = 0;
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assign TrapM = 0;
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assign ITLBFlushF = 0;
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assign ITLBFlushF = 0;
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assign DTLBFlushM = 0;
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assign DTLBFlushM = 0;
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end
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end
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if (`M_SUPPORTED) begin:mdu
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if (`M_SUPPORTED) begin:mdu
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muldiv mdu(
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muldiv mdu(
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.clk, .reset,
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.clk, .reset,
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.ForwardedSrcAE, .ForwardedSrcBE,
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.ForwardedSrcAE, .ForwardedSrcBE,
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.Funct3E, .Funct3M, .MulDivE, .W64E,
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.Funct3E, .Funct3M, .MulDivE, .W64E,
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.MulDivResultW, .DivBusyE,
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.MulDivResultW, .DivBusyE,
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.StallM, .StallW, .FlushM, .FlushW
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.StallM, .StallW, .FlushM, .FlushW
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);
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);
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end else begin // no M instructions supported
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end else begin // no M instructions supported
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assign MulDivResultW = 0;
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assign MulDivResultW = 0;
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assign DivBusyE = 0;
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assign DivBusyE = 0;
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end
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end
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if (`F_SUPPORTED) begin:fpu
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if (`F_SUPPORTED) begin:fpu
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fpu fpu(
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fpu fpu(
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.clk, .reset,
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.clk, .reset,
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.FRM_REGW, // Rounding mode from CSR
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.FRM_REGW, // Rounding mode from CSR
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.InstrD, // instruction from IFU
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.InstrD, // instruction from IFU
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.ReadDataW,// Read data from memory
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.ReadDataW,// Read data from memory
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.ForwardedSrcAE, // Integer input being processed (from IEU)
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.ForwardedSrcAE, // Integer input being processed (from IEU)
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.StallE, .StallM, .StallW, // stall signals from HZU
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.StallE, .StallM, .StallW, // stall signals from HZU
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.FlushE, .FlushM, .FlushW, // flush signals from HZU
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.FlushE, .FlushM, .FlushW, // flush signals from HZU
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.RdM, .RdW, // which FP register to write to (from IEU)
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.RdM, .RdW, // which FP register to write to (from IEU)
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.FRegWriteM, // FP register write enable
|
.FRegWriteM, // FP register write enable
|
||||||
.FStallD, // Stall the decode stage
|
.FStallD, // Stall the decode stage
|
||||||
.FWriteIntE, // integer register write enable
|
.FWriteIntE, // integer register write enable
|
||||||
.FWriteDataE, // Data to be written to memory
|
.FWriteDataE, // Data to be written to memory
|
||||||
.FIntResM, // data to be written to integer register
|
.FIntResM, // data to be written to integer register
|
||||||
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
|
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
|
||||||
.IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
|
.IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
|
||||||
.SetFflagsM // FPU flags (to privileged unit)
|
.SetFflagsM // FPU flags (to privileged unit)
|
||||||
); // floating point unit
|
); // floating point unit
|
||||||
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
|
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
|
||||||
assign FStallD = 0;
|
assign FStallD = 0;
|
||||||
assign FWriteIntE = 0;
|
assign FWriteIntE = 0;
|
||||||
assign FWriteDataE = 0;
|
assign FWriteDataE = 0;
|
||||||
assign FIntResM = 0;
|
assign FIntResM = 0;
|
||||||
assign FDivBusyE = 0;
|
assign FDivBusyE = 0;
|
||||||
assign IllegalFPUInstrD = 1;
|
assign IllegalFPUInstrD = 1;
|
||||||
assign SetFflagsM = 0;
|
assign SetFflagsM = 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
endgenerate
|
|
||||||
// Priveleged block operates in M and W stages, handling CSRs and exceptions
|
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -121,11 +121,9 @@ module sdModel
|
|||||||
integer sdModel_file_desc;
|
integer sdModel_file_desc;
|
||||||
|
|
||||||
genvar i;
|
genvar i;
|
||||||
generate
|
for(i=0; i<4; i=i+1) begin:CRC_16_gen
|
||||||
for(i=0; i<4; i=i+1) begin:CRC_16_gen
|
sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);
|
||||||
sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);
|
end
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
sd_crc_7 crc_7
|
sd_crc_7 crc_7
|
||||||
(
|
(
|
||||||
|
@ -763,17 +763,12 @@ string tests32f[] = '{
|
|||||||
.done(DCacheFlushDone));
|
.done(DCacheFlushDone));
|
||||||
|
|
||||||
|
|
||||||
generate
|
// initialize the branch predictor
|
||||||
// initialize the branch predictor
|
if (`BPRED_ENABLED == 1)
|
||||||
if (`BPRED_ENABLED == 1) begin : bpred
|
initial begin
|
||||||
|
$readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
|
||||||
initial begin
|
$readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
||||||
$readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
|
|
||||||
$readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
endgenerate
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module riscvassertions();
|
module riscvassertions();
|
||||||
@ -830,29 +825,26 @@ module DCacheFlushFSM
|
|||||||
|
|
||||||
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
|
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
|
||||||
|
|
||||||
generate
|
for(index = 0; index < numlines; index++) begin
|
||||||
for(index = 0; index < numlines; index++) begin
|
for(way = 0; way < numways; way++) begin
|
||||||
for(way = 0; way < numways; way++) begin
|
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||||
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
copyShadow #(.tagstart(tagstart), .loglinebytelen(loglinebytelen))
|
||||||
copyShadow #(.tagstart(tagstart),
|
copyShadow(.clk,
|
||||||
.loglinebytelen(loglinebytelen))
|
.start,
|
||||||
copyShadow(.clk,
|
.tag(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||||
.start,
|
.valid(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].ValidBits[index]),
|
||||||
.tag(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
.dirty(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
|
||||||
.valid(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].ValidBits[index]),
|
.data(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||||
.dirty(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
|
.index(index),
|
||||||
.data(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
.cacheWord(cacheWord),
|
||||||
.index(index),
|
.CacheData(CacheData[way][index][cacheWord]),
|
||||||
.cacheWord(cacheWord),
|
.CacheAdr(CacheAdr[way][index][cacheWord]),
|
||||||
.CacheData(CacheData[way][index][cacheWord]),
|
.CacheTag(CacheTag[way][index][cacheWord]),
|
||||||
.CacheAdr(CacheAdr[way][index][cacheWord]),
|
.CacheValid(CacheValid[way][index][cacheWord]),
|
||||||
.CacheTag(CacheTag[way][index][cacheWord]),
|
.CacheDirty(CacheDirty[way][index][cacheWord]));
|
||||||
.CacheValid(CacheValid[way][index][cacheWord]),
|
|
||||||
.CacheDirty(CacheDirty[way][index][cacheWord]));
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endgenerate
|
end
|
||||||
|
|
||||||
integer i, j, k;
|
integer i, j, k;
|
||||||
|
|
||||||
|
@ -22,7 +22,7 @@
|
|||||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
|
||||||
// When letting Wally go for it, let wally generate own interrupts
|
// When letting Wally go for it, let wally make own interrupts
|
||||||
///////////////////////////////////////////
|
///////////////////////////////////////////
|
||||||
|
|
||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
@ -280,13 +280,6 @@ module testbench;
|
|||||||
|
|
||||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
|
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
|
||||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3);
|
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3);
|
||||||
generate
|
|
||||||
genvar i;
|
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
|
||||||
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPCFG, [7:0],`PMP_ENTRIES-1,0);
|
|
||||||
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPADDR, [`XLEN-1:0],`PMP_ENTRIES-1,0);
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
endgenerate
|
|
||||||
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
|
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
|
||||||
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
|
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
|
||||||
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
|
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
|
||||||
|
@ -296,13 +296,8 @@ logic [3:0] dummy;
|
|||||||
// or sw gp, -56(t0)
|
// or sw gp, -56(t0)
|
||||||
// or on a jump to self infinite loop (6f) for RISC-V Arch tests
|
// or on a jump to self infinite loop (6f) for RISC-V Arch tests
|
||||||
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
|
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
|
||||||
generate
|
if (`ZICSR_SUPPORTED) assign ecf = dut.hart.priv.priv.EcallFaultM;
|
||||||
if (`ZICSR_SUPPORTED) begin
|
else assign ecf = 0;
|
||||||
assign ecf = dut.hart.priv.priv.EcallFaultM;
|
|
||||||
end else begin
|
|
||||||
assign ecf = 0;
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
assign DCacheFlushStart = ecf &
|
assign DCacheFlushStart = ecf &
|
||||||
(dut.hart.ieu.dp.regf.rf[3] == 1 |
|
(dut.hart.ieu.dp.regf.rf[3] == 1 |
|
||||||
(dut.hart.ieu.dp.regf.we3 &
|
(dut.hart.ieu.dp.regf.we3 &
|
||||||
@ -310,24 +305,17 @@ logic [3:0] dummy;
|
|||||||
dut.hart.ieu.dp.regf.wd3 == 1)) |
|
dut.hart.ieu.dp.regf.wd3 == 1)) |
|
||||||
(dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
|
(dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
|
||||||
|
|
||||||
// **** Fix when the check in the shadow ram is fixed.
|
|
||||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
.start(DCacheFlushStart),
|
.start(DCacheFlushStart),
|
||||||
.done(DCacheFlushDone));
|
.done(DCacheFlushDone));
|
||||||
|
|
||||||
|
// initialize the branch predictor
|
||||||
generate
|
if (`BPRED_ENABLED == 1)
|
||||||
// initialize the branch predictor
|
initial begin
|
||||||
if (`BPRED_ENABLED == 1) begin : bpred
|
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
|
||||||
|
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
||||||
initial begin
|
|
||||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
|
|
||||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
endgenerate
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module riscvassertions;
|
module riscvassertions;
|
||||||
@ -370,7 +358,6 @@ module DCacheFlushFSM
|
|||||||
|
|
||||||
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
|
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
|
||||||
|
|
||||||
generate
|
|
||||||
if(`MEM_DCACHE) begin
|
if(`MEM_DCACHE) begin
|
||||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
|
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
|
||||||
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
|
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
|
||||||
@ -430,15 +417,7 @@ module DCacheFlushFSM
|
|||||||
|
|
||||||
|
|
||||||
end
|
end
|
||||||
endgenerate
|
flop #(1) doneReg(.clk, .d(start), .q(done));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
flop #(1) doneReg(.clk(clk),
|
|
||||||
.d(start),
|
|
||||||
.q(done));
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module copyShadow
|
module copyShadow
|
||||||
|
Loading…
Reference in New Issue
Block a user