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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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David Harris 2021-04-23 19:04:29 -04:00
commit 85eb6bcf1a
1 changed files with 18 additions and 11 deletions
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29
wally-pipelined/testbench/testbench-busybear.sv
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@ -1,5 +1,13 @@
`include "wally-config.vh" `include "wally-config.vh"
function logic [`XLEN-1:0] adrTranslator(
input logic [`XLEN-1:0] adrIn);
begin
// MMU team put translation here!!
assign adrTranslator = adrIn;
end
endfunction
module testbench_busybear(); module testbench_busybear();
logic clk, reset; logic clk, reset;
@ -68,7 +76,7 @@ module testbench_busybear();
// read CSR trace file // read CSR trace file
integer data_file_csr, scan_file_csr; integer data_file_csr, scan_file_csr;
initial begin initial begin
data_file_csr = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedCSRs.txt"}, "r"); data_file_csr = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedCSRs2.txt"}, "r");
if (data_file_csr == 0) begin if (data_file_csr == 0) begin
$display("file couldn't be opened"); $display("file couldn't be opened");
$stop; $stop;
@ -189,7 +197,7 @@ module testbench_busybear();
logic [63:0] readMask; logic [63:0] readMask;
assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0]; assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0];
logic [`XLEN-1:0] readAdrExpected; logic [`XLEN-1:0] readAdrExpected, readAdrTranslated;
import ahbliteState::*; import ahbliteState::*;
always @(dut.HRDATA) begin always @(dut.HRDATA) begin
@ -204,8 +212,9 @@ module testbench_busybear();
end end
scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected); scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA); scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
if (~equal(HADDR,readAdrExpected,4)) begin assign readAdrTranslated = adrTranslator(readAdrExpected);
$display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected); if (~equal(HADDR,readAdrTranslated,4)) begin
$display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrTranslated);
`ERROR `ERROR
end end
if ((readMask & HRDATA) !== (readMask & dut.HRDATA)) begin if ((readMask & HRDATA) !== (readMask & dut.HRDATA)) begin
@ -227,7 +236,7 @@ module testbench_busybear();
end end
logic [`XLEN-1:0] writeDataExpected, writeAdrExpected; logic [`XLEN-1:0] writeDataExpected, writeAdrExpected, writeAdrTranslated;
// this might need to change // this might need to change
//always @(HWDATA or HADDR or HSIZE or HWRITE) begin //always @(HWDATA or HADDR or HSIZE or HWRITE) begin
@ -240,12 +249,14 @@ module testbench_busybear();
end end
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
assign writeAdrTranslated = adrTranslator(writeAdrExpected);
if (writeDataExpected != HWDATA) begin if (writeDataExpected != HWDATA) begin
$display("%0t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected); $display("%0t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
`ERROR `ERROR
end end
if (~equal(writeAdrExpected,HADDR,1)) begin if (~equal(writeAdrTranslated,HADDR,1)) begin
$display("%0t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected); $display("%0t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrTranslated);
`ERROR `ERROR
end end
end end
@ -346,10 +357,6 @@ module testbench_busybear();
//$stop; //$stop;
generate generate
if (`BUSYBEAR == 1) begin if (`BUSYBEAR == 1) begin
initial begin
#34140421;
$stop;
end
initial begin //this is temporary until the bug can be fixed!!! initial begin //this is temporary until the bug can be fixed!!!
#11130100; #11130100;
force dut.hart.ieu.dp.regf.rf[5] = 64'h0000000080000004; force dut.hart.ieu.dp.regf.rf[5] = 64'h0000000080000004;