Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

wally-pipelined/config/busybear/wally-config.vh

@@ -63,16 +63,21 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define TIMBASE       32'h80000000
-`define TIMRANGE      32'h07FFFFFF
 `define BOOTTIMBASE   32'h00000000 //only needs to go from 0x1000 to 0x2FFF, extending to a power of 2
 `define BOOTTIMRANGE  32'h00003FFF
 `define CLINTBASE     32'h02000000
-`define CLINTRANGE    32'h0000BFFF
+`define CLINTRANGE    32'h0000FFFF
-//`define GPIOBASE    32'h10012000 // no GPIO in linux for now
+`define PLICBASE      32'h0C000000
-//`define GPIORANGE   32'h000000FF
+`define PLICRANGE     32'h0FFFFFFF
 `define UARTBASE      32'h10000000
 `define UARTRANGE     32'h00000007
+`define VBD0BASE      32'h10001000
+`define VBD0RANGE     32'h000001FF
+// differing from Imperas' OVPSim by not having a VND0
+`define GPIOBASE      32'h20000000 
+`define GPIORANGE     32'h000000FF
+`define TIMBASE       32'h80000000
+`define TIMRANGE      32'h07FFFFFF
 // Bus Interface width
 `define AHBW 64
 
@@ -81,6 +86,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 1
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/coremark/wally-config.vh

@@ -66,6 +66,8 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
+`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h00000000
 `define TIMRANGE   32'hFFFFFFFF
 `define CLINTBASE  32'h02000000
@@ -80,6 +82,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/coremark_bare/wally-config.vh

@@ -66,6 +66,8 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
+`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h80000000
 `define TIMRANGE   32'h000FFFFF
 `define CLINTBASE  32'h02000000
@@ -80,6 +82,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/rv32ic/wally-config.vh

@@ -62,6 +62,8 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
+`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h80000000
 `define TIMRANGE   32'h0007FFFF
 `define CLINTBASE  32'h02000000
@@ -79,6 +81,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/rv64ic/wally-config.vh

@@ -66,6 +66,8 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
+`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h80000000
 `define TIMRANGE   32'h0007FFFF
 `define CLINTBASE  32'h02000000
@@ -80,6 +82,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/rv64icfd/wally-config.vh

@@ -66,6 +66,8 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
+`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h80000000
 `define TIMRANGE   32'h0007FFFF
 `define CLINTBASE  32'h02000000
@@ -80,6 +82,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/regression/wally-coremark_bare.do

@@ -111,6 +111,6 @@ set DefaultRadix hexadecimal
 -- Run the Simulation 
 #run 7402000
 #run 12750
-#run -all
+run -all
-run 5000
+#run 21400
 #quit

wally-pipelined/src/privileged/csrm.sv

@@ -125,11 +125,12 @@ module csrm #(parameter
   flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); 
   flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); 
   flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
-  `ifndef BUSYBEAR
+  generate
-  flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], allones, MCOUNTEREN_REGW);
+    if (`OVPSIM_CSR_CONFIG)
-  `else
       flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW);
-  `endif
+    else
+      flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], allones, MCOUNTEREN_REGW);
+  endgenerate
   flopenl #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], allones, MCOUNTINHIBIT_REGW);
   flopenr #(`XLEN) PMPADDR0reg(clk, reset, WritePMPADDR0M, CSRWriteValM, PMPADDR0_REGW);  
   // PMPCFG registers are a pair of 64-bit in RV64 and four 32-bit in RV32

wally-pipelined/src/privileged/csrs.sv

@@ -82,11 +82,10 @@ module csrs #(parameter
       flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, zero, SCAUSE_REGW); 
       flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
       flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
-      `ifndef BUSYBEAR
+      if (`OVPSIM_CSR_CONFIG)
-      flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW);
-      `else
         flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW);
-      `endif
+      else
+        flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW);
       if (`N_SUPPORTED) begin
         logic WriteSEDELEGM, WriteSIDELEGM;
         assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG);

wally-pipelined/src/uncore/imem.sv

@@ -33,9 +33,7 @@ module imem (
 
  /* verilator lint_off UNDRIVEN */
   logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE+`TIMBASE)>>(1+`XLEN/32)];
-  `ifdef BOOTTIMBASE
   logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)];
-  `endif
  /* verilator lint_on UNDRIVEN */
   logic [31:0] adrbits; // needs to be 32 bits to index RAM
   logic [`XLEN-1:0] rd;
@@ -46,21 +44,13 @@ module imem (
     else          assign adrbits = AdrF[31:3];
   endgenerate
 
-  `ifndef BOOTTIMBASE
-  assign #2 rd = RAM[adrbits]; // word aligned
-  `else
   assign #2 rd = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options
-  `endif
 
   // hack right now for unaligned 32-bit instructions
   // eventually this will need to cause a stall like a cache miss
   // when the instruction wraps around a cache line
   // could be optimized to only stall when the instruction wrapping is 32 bits
-  `ifndef BOOTTIMBASE
-  assign #2 rd2 = RAM[adrbits+1][15:0];
-  `else
   assign #2 rd2 = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options
-  `endif
   generate 
     if (`XLEN==32) begin
       assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd;
@@ -68,9 +58,11 @@ module imem (
     end else begin
       assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32])
                           : (AdrF[1] ? rd[47:16] : rd[31:0]);
-      `ifndef BOOTTIMBASE
+      `ifndef BUSYBEAR
       assign InstrAccessFaultF = |AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIMBASE | `TIMRANGE);
       `else
+      // *** this is just a hack since the logic above seems scary ***
+      // TODO: this should be removed when InstrAccessFaultF works with bootram also
       assign InstrAccessFaultF = 0; //busybear: for now, i know we're not doing this
       `endif
     end

wally-pipelined/src/uncore/uncore.sv

@@ -64,23 +64,17 @@ module uncore (
   logic            HSELTimD, HSELCLINTD, HSELGPIOD, HSELUARTD;
   logic            HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART;
   logic            HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART;  
-  `ifdef BOOTTIMBASE
   logic [`XLEN-1:0] HREADBootTim; 
   logic            HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim;
   logic [1:0]      MemRWboottim;
-  `endif
   logic            UARTIntr;// *** will need to tie INTR to an interrupt handler
   
 
   // AHB Address decoder
   adrdec timdec(HADDR, `TIMBASE, `TIMRANGE, HSELTim);
-  `ifdef BOOTTIMBASE
   adrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, HSELBootTim);
-  `endif
   adrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, HSELCLINT);
-  `ifdef GPIOBASE
   adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO); 
-  `endif
   adrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, PreHSELUART);
   assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported
 
@@ -89,15 +83,11 @@ module uncore (
 
   // tightly integrated memory
   dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) dtim (.*);
-  `ifdef BOOTTIMBASE
   dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
-  `endif
 
   // memory-mapped I/O peripherals
   clint clint(.HADDR(HADDR[15:0]), .*);
-  `ifdef GPIOBASE
   gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts
-  `endif
   uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
             .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), 
             .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
@@ -105,50 +95,22 @@ module uncore (
   // mux could also include external memory  
   // AHB Read Multiplexer
   assign HRDATA = ({`XLEN{HSELTimD}} & HREADTim) | ({`XLEN{HSELCLINTD}} & HREADCLINT) | 
-                    `ifdef GPIOBASE
+                     ({`XLEN{HSELGPIOD}} & HREADGPIO) | ({`XLEN{HSELBootTimD}} & HREADBootTim) |
-                     ({`XLEN{HSELGPIOD}} & HREADGPIO) |
-                    `endif
-                    `ifdef BOOTTIMBASE
-                     ({`XLEN{HSELBootTimD}} & HREADBootTim) |
-                    `endif
                      ({`XLEN{HSELUARTD}} & HREADUART);
-  assign HRESP = HSELTimD & HRESPTim | HSELCLINTD & HRESPCLINT | 
+  assign HRESP = HSELTimD & HRESPTim | HSELCLINTD & HRESPCLINT | HSELGPIOD & HRESPGPIO | 
-                 `ifdef GPIOBASE
+                 HSELBootTimD & HRESPBootTim | HSELUARTD & HRESPUART;
-                 HSELGPIOD & HRESPGPIO | 
+  assign HREADY = HSELTimD & HREADYTim | HSELCLINTD & HREADYCLINT | HSELGPIOD & HREADYGPIO | 
-                 `endif
+                  HSELBootTimD & HREADYBootTim | HSELUARTD & HREADYUART;
-                 `ifdef BOOTTIMBASE
-                 HSELBootTimD & HRESPBootTim | 
-                 `endif
-                 HSELUARTD & HRESPUART;
-  assign HREADY = HSELTimD & HREADYTim | HSELCLINTD & HREADYCLINT | 
-                  `ifdef GPIOBASE
-                  HSELGPIOD & HREADYGPIO | 
-                  `endif
-                  `ifdef BOOTTIMBASE
-                  HSELBootTimD & HREADYBootTim | 
-                  `endif
-                  HSELUARTD & HREADYUART;
 
   // Faults
-  assign DataAccessFaultM = ~(HSELTimD | HSELCLINTD | 
+  assign DataAccessFaultM = ~(HSELTimD | HSELCLINTD | HSELGPIOD | HSELBootTimD | HSELUARTD);
-                            `ifdef GPIOBASE
-                            HSELGPIOD |
-                            `endif
-                            `ifdef BOOTTIMBASE
-                            HSELBootTimD |
-                            `endif
-                            HSELUARTD);
 
 
   // Address Decoder Delay (figure 4-2 in spec)
   flopr #(1) hseltimreg(HCLK, ~HRESETn, HSELTim, HSELTimD);
   flopr #(1) hselclintreg(HCLK, ~HRESETn, HSELCLINT, HSELCLINTD);
-  `ifdef GPIOBASE
   flopr #(1) hselgpioreg(HCLK, ~HRESETn, HSELGPIO, HSELGPIOD);
-  `endif
   flopr #(1) hseluartreg(HCLK, ~HRESETn, HSELUART, HSELUARTD);
-  `ifdef BOOTTIMBASE
   flopr #(1) hselboottimreg(HCLK, ~HRESETn, HSELBootTim, HSELBootTimD);
-  `endif
 endmodule
 

wally-pipelined/testbench/testbench-coremark_bare.sv

@@ -48,7 +48,7 @@ module testbench();
   
   // pick tests based on modes supported
   initial 
-  tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"};
+  tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"};
   string signame, memfilename;
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
@@ -76,8 +76,8 @@ module testbench();
       $readmemh(memfilename, dut.uncore.dtim.RAM);
       for(j=268437829; j < 268566528; j = j+1)
         dut.uncore.dtim.RAM[j] = 64'b0;
-//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr";
+//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
-//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab";
+//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
       reset = 1; # 22; reset = 0;
     end
   // generate clock to sequence tests