Simplified and clarified names in cacheLRU.

src/cache/cache.sv

@@ -180,14 +180,14 @@ module cache import cvw::*; #(parameter cvw_t P,
 
     assign DemuxedByteMask = BlankByteMask << ((MUXINTERVAL/8) * WordOffsetAddr);
 
-    assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask;  // If load miss set all muxes to 1.
+    assign FetchBufferByteSel = SetDirty ? ~DemuxedByteMask : '1;  // If load miss set all muxes to 1.
 
     // Merge write data into fetched cache line for store miss
     for(index = 0; index < LINELEN/8; index++) begin
       mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
         .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index] & ~CMOpM[3]), .y(LineWriteData[8*index+7:8*index]));
     end
-    assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
+    assign LineByteMask = SetDirty ? DemuxedByteMask : '1;
   end
   else
     begin:WriteSelLogic

src/cache/cacheLRU.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // cacheLRU.sv
 //
-// Written: Ross Thompson ross1728@gmail.com
+// Written: Rose Thompson ross1728@gmail.com
 // Created: 20 July 2021
 // Modified: 20 January 2023
 //
@@ -51,23 +51,27 @@ module cacheLRU
   logic [NUMWAYS-2:0]                  LRUMemory [NUMLINES-1:0];
   logic [NUMWAYS-2:0]                  CurrLRU;
   logic [NUMWAYS-2:0]                  NextLRU;
-  logic [NUMWAYS-1:0]                  Way;
+  logic [LOGNUMWAYS-1:0]               HitWayEncoded, Way;
-  logic [LOGNUMWAYS-1:0]               WayEncoded;
   logic [NUMWAYS-2:0]                  WayExpanded;
   logic                                AllValid;
   
   genvar                               row;
 
   /* verilator lint_off UNOPTFLAT */
-  // Ross: For some reason verilator does not like this.  I checked and it is not a circular path.
+  // Rose: For some reason verilator does not like this.  I checked and it is not a circular path.
   logic [NUMWAYS-2:0]                  LRUUpdate;
   logic [LOGNUMWAYS-1:0] Intermediate [NUMWAYS-2:0];
   /* verilator lint_on UNOPTFLAT */
 
+  logic [NUMWAYS-1:0] FirstZero;
+  logic [LOGNUMWAYS-1:0] FirstZeroWay;
+  logic [LOGNUMWAYS-1:0] VictimWayEnc;
+
+  binencoder #(NUMWAYS) hitwayencoder(HitWay, HitWayEncoded);
+
   assign AllValid = &ValidWay;
 
   ///// Update replacement bits.
-
   // coverage off
   // Excluded from coverage b/c it is untestable without varying NUMWAYS.
   function integer log2 (integer value);
@@ -80,8 +84,7 @@ module cacheLRU
   // coverage on
 
   // On a miss we need to ignore HitWay and derive the new replacement bits with the VictimWay.
-  mux2 #(NUMWAYS) WayMux(HitWay, VictimWay, SetValid, Way);
+  mux2 #(LOGNUMWAYS) WayMuxEnc(HitWayEncoded, VictimWayEnc, SetValid, Way);
-  binencoder #(NUMWAYS) encoder(Way, WayEncoded);
 
   // bit duplication
   // expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ...
@@ -89,7 +92,7 @@ module cacheLRU
     localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1);
     localparam StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
     localparam EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
-    assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}};
+    assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{Way[row]}};
   end
 
   genvar               node;
@@ -102,14 +105,14 @@ module cacheLRU
     localparam r = LOGNUMWAYS - ctr_depth;
 
     // the child node will be updated if its parent was updated and
-    // the WayEncoded bit was the correct value.
+    // the Way bit was the correct value.
     // The if statement is only there for coverage since LRUUpdate[root] is always 1.
     if (node == NUMWAYS-2) begin
-      assign LRUUpdate[lchild] = ~WayEncoded[r];
+      assign LRUUpdate[lchild] = ~Way[r];
-      assign LRUUpdate[rchild] = WayEncoded[r];
+      assign LRUUpdate[rchild] = Way[r];
     end else begin
-      assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r];
+      assign LRUUpdate[lchild] = LRUUpdate[node] & ~Way[r];
-      assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r];
+      assign LRUUpdate[rchild] = LRUUpdate[node] & Way[r];
     end
   end
 
@@ -129,14 +132,10 @@ module cacheLRU
     assign Intermediate[node] = CurrLRU[node] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
   end
 
-  logic [NUMWAYS-1:0] FirstZero;
-  logic [LOGNUMWAYS-1:0] FirstZeroWay;
-  logic [LOGNUMWAYS-1:0] VictimWayEnc;
   
   priorityonehot #(NUMWAYS) FirstZeroEncoder(~ValidWay, FirstZero);
   binencoder #(NUMWAYS) FirstZeroWayEncoder(FirstZero, FirstZeroWay);
   mux2 #(LOGNUMWAYS) VictimMux(FirstZeroWay, Intermediate[NUMWAYS-2], AllValid, VictimWayEnc);
-  //decoder #(LOGNUMWAYS) decoder (Intermediate[NUMWAYS-2], VictimWay);
   decoder #(LOGNUMWAYS) decoder (VictimWayEnc, VictimWay);
 
   // LRU storage must be reset for modelsim to run. However the reset value does not actually matter in practice.