Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 02:05:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

busybear testbench: test on first 100k instrs

Browse Source 
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
This commit is contained in:
Noah Boorstin 2021-01-29 00:13:14 -05:00
parent aedadb7703
commit 84e4193db6
2 changed files with 8 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wally-pipelined/regression/wally-busybear.do
View File

@ -131,6 +131,6 @@ add wave /testbench_busybear/InstrWName
#set DefaultRadix hexadecimal #set DefaultRadix hexadecimal
# #
#-- Run the Simulation #-- Run the Simulation
run 129812 run 621070
#run -all #run -all
##quit ##quit

13
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -90,7 +90,7 @@ module testbench_busybear();
scan_file_rf = $fscanf(data_file_rf, "%x\n", rfExpected[j]); scan_file_rf = $fscanf(data_file_rf, "%x\n", rfExpected[j]);
// check things! // check things!
if (rf[j*64+63 -: 64] != rfExpected[j]) begin if (rf[j*64+63 -: 64] != rfExpected[j]) begin
$display("%t ps: rf[%0d] does not equal rf expected: %x, %x", $time, j, rf[j*64+63 -: 64], rfExpected[j]); $display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, j, rf[j*64+63 -: 64], rfExpected[j]);
// $stop; // $stop;
end end
end end
@ -107,7 +107,7 @@ module testbench_busybear();
scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected); scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
scan_file_memR = $fscanf(data_file_memR, "%x\n", ReadDataM); scan_file_memR = $fscanf(data_file_memR, "%x\n", ReadDataM);
if (DataAdrM != readAdrExpected) begin if (DataAdrM != readAdrExpected) begin
$display("%t ps: DataAdrM does not equal readAdrExpected: %x, %x", $time, DataAdrM, readAdrExpected); $display("%t ps, instr %0d: DataAdrM does not equal readAdrExpected: %x, %x", $time, instrs, DataAdrM, readAdrExpected);
end end
end end
end end
@ -126,12 +126,12 @@ module testbench_busybear();
for(int i=0; i<8; i++) begin for(int i=0; i<8; i++) begin
if (ByteMaskM[i]) begin if (ByteMaskM[i]) begin
if (writeDataExpected[i*8+7 -: 8] != WriteDataM[i*8+7 -: 8]) begin if (writeDataExpected[i*8+7 -: 8] != WriteDataM[i*8+7 -: 8]) begin
$display("%t ps: WriteDataM does not equal writeDataExpected: %x, %x", $time, WriteDataM, writeDataExpected); $display("%t ps, instr %0d: WriteDataM does not equal writeDataExpected: %x, %x", $time, instrs, WriteDataM, writeDataExpected);
end end
end end
end end
if (writeAdrExpected != DataAdrM) begin if (writeAdrExpected != DataAdrM) begin
$display("%t ps: DataAdrM does not equal writeAdrExpected: %x, %x", $time, DataAdrM, writeAdrExpected); $display("%t ps, instr %0d: DataAdrM does not equal writeAdrExpected: %x, %x", $time, instrs, DataAdrM, writeAdrExpected);
end end
end end
end end
@ -171,7 +171,8 @@ module testbench_busybear();
// then expected PC value // then expected PC value
scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected); scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) || if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0)) begin (instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
(instrs <= 100000 && instrs % 10000 == 0)) begin
$display("loaded %0d instructions", instrs); $display("loaded %0d instructions", instrs);
end end
instrs += 1; instrs += 1;
@ -195,7 +196,7 @@ module testbench_busybear();
//check things! //check things!
if ((~speculative) && (PCF !== pcExpected)) begin if ((~speculative) && (PCF !== pcExpected)) begin
$display("%t ps: PC does not equal PC expected: %x, %x", $time, PCF, pcExpected); $display("%t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
// $stop; // $stop;
end end
end end