From 9a59c8e07f79b70dd7ec59a2f8ef1ff9572563e6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 20 Jun 2024 23:46:45 -0700 Subject: [PATCH 01/10] reduced bit widths for integer on fpu --- config/shared/config-shared.vh | 8 +++++++- config/shared/parameter-defs.vh | 6 +++++- src/cvw.sv | 6 ++++++ src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 20 +++++++++++++------- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 6 +++--- 5 files changed, 34 insertions(+), 12 deletions(-) diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 44bf77eac..08b8ab739 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -97,13 +97,19 @@ localparam RK = LOGR*DIVCOPIES; // r*k bits localparam FPDIVMINb = NF + 2; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right localparam DIVMINb = ((FPDIVMINb>> IntNormShiftM); // special case logic diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 9156005fd..737d9089a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -119,7 +119,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( ////////////////////////////////////////////////////// if (P.IDIV_ON_FPU) begin:intrightshift // Int Supported - logic [P.DIVBLEN-1:0] ZeroDiff, p; + logic [P.DIVBLEN-1:0] ZeroDiff,p; // calculate number of fractional bits p assign ZeroDiff = mE - ell; // Difference in number of leading zeros @@ -218,8 +218,8 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( logic RemOpE; /* verilator lint_off WIDTH */ - assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. n = (Cycles * k - 1) - assign IntRemNormShiftE = mE + (P.DIVb-(P.XLEN-1)); // m + b - (N-1) for remainder normalization shift + assign IntDivNormShiftE = P.INTDIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. n = (Cycles * k - 1) + assign IntRemNormShiftE = mE + (P.INTDIVb-(P.XLEN-1)); // m + b - (N-1) for remainder normalization shift /* verilator lint_on WIDTH */ assign RemOpE = Funct3E[1]; mux2 #(P.DIVBLEN) normshiftmux(IntDivNormShiftE, IntRemNormShiftE, RemOpE, IntNormShiftE); From 00bf3faa9cd9c039b898ee3bdad7588ed0c4d096 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 21 Jun 2024 21:31:19 -0700 Subject: [PATCH 02/10] changed intdivb width --- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 5 +++-- testbench/tests.vh | 10 +++++----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 5e0800b4d..0a036eb06 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -45,7 +45,8 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] FIntDivResultM // U/Q(XLEN.0) ); - logic [P.DIVb+3:0] W, Sum; + logic [P.DIVb+3:0] Sum; + logic [P.INTDIVb+3:0] W; logic [P.DIVb:0] PreUmM; logic NegStickyM; logic weq0E, WZeroM; @@ -105,7 +106,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( assign SumTrunc = Sum[P.DIVb+3:P.DIVb-P.INTDIVb]; assign DTrunc = D[P.DIVb+3:P.DIVb-P.INTDIVb]; - assign W = $signed(Sum) >>> P.LOGR; + assign W = $signed(SumTrunc) >>> P.LOGR; assign UnsignedQuotM = {3'b000, PreUmM[P.DIVb:P.DIVb-P.INTDIVb]}; diff --git a/testbench/tests.vh b/testbench/tests.vh index 279f765be..0a81c7b94 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1125,11 +1125,11 @@ string imperas32f[] = '{ "rv64i_m/M/src/divu-01.S", "rv64i_m/M/src/divuw-01.S", "rv64i_m/M/src/divw-01.S", - "rv64i_m/M/src/mul-01.S", - "rv64i_m/M/src/mulh-01.S", - "rv64i_m/M/src/mulhsu-01.S", - "rv64i_m/M/src/mulhu-01.S", - "rv64i_m/M/src/mulw-01.S", + //"rv64i_m/M/src/mul-01.S", + //"rv64i_m/M/src/mulh-01.S", + //"rv64i_m/M/src/mulhsu-01.S", + //"rv64i_m/M/src/mulhu-01.S", + //"rv64i_m/M/src/mulw-01.S", "rv64i_m/M/src/rem-01.S", "rv64i_m/M/src/remu-01.S", "rv64i_m/M/src/remuw-01.S", From e6dc50308adf71d2e5d8fbfcf25bd36598b8474c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 21 Jun 2024 21:50:55 -0700 Subject: [PATCH 03/10] integer postprocessing hardware matches diagram --- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 0a036eb06..b97056b70 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -45,7 +45,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] FIntDivResultM // U/Q(XLEN.0) ); - logic [P.DIVb+3:0] Sum; + logic [P.DIVb+3:0] um, Sum; logic [P.INTDIVb+3:0] W; logic [P.DIVb:0] PreUmM; logic NegStickyM; @@ -112,13 +112,13 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( // Integer remainder: sticky and sign correction muxes assign NegQuotM = AsM ^ BsM; // Integer Quotient is negative - mux2 #(P.INTDIVb+4) normremdmux(W, W+D, NegStickyM, NormRemDM); - mux2 #(P.INTDIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM); - mux2 #(P.INTDIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM); + mux2 #(P.INTDIVb+4) normremdmux(W, W+DTrunc, NegStickyM, NormRemDM); + // Select quotient or remainder and do normalization shift - mux2 #(P.INTDIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM); - assign PreIntResultM = $signed(PreResultM >>> IntNormShiftM); + mux2 #(P.INTDIVb+4) presresultmux(UnsignedQuotM, NormRemDM, RemOpM, PreResultM); + assign PreResultShiftedM = PreResultM >> IntNormShiftM; + mux2 #(P.INTDIVb+4) preintresultmux(PreResultShiftedM, -PreResultShiftedM,AsM ^ (BsM&~RemOpM), PreIntResultM); // special case logic // terminates immediately when B is Zero (div 0) or |A| has more leading 0s than |B| From 19f0cf7a350257735c147b81d6fbe9c8e35980f3 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 21 Jun 2024 21:51:44 -0700 Subject: [PATCH 04/10] putting back tests in tests vh --- testbench/tests.vh | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 0a81c7b94..8b3352187 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1125,11 +1125,11 @@ string imperas32f[] = '{ "rv64i_m/M/src/divu-01.S", "rv64i_m/M/src/divuw-01.S", "rv64i_m/M/src/divw-01.S", - //"rv64i_m/M/src/mul-01.S", - //"rv64i_m/M/src/mulh-01.S", - //"rv64i_m/M/src/mulhsu-01.S", - //"rv64i_m/M/src/mulhu-01.S", - //"rv64i_m/M/src/mulw-01.S", + "rv64i_m/M/src/mul-01.S", + "rv64i_m/M/src/mulh-01.S", + "rv64i_m/M/src/mulhsu-01.S", + "rv64i_m/M/src/mulhu-01.S", + "rv64i_m/M/src/mulw-01.S", "rv64i_m/M/src/rem-01.S", "rv64i_m/M/src/remu-01.S", "rv64i_m/M/src/remuw-01.S", @@ -1802,7 +1802,6 @@ string imperas32f[] = '{ }; - string arch64d_fma[] = '{ `RISCVARCHTEST, //"rv64i_m/D/src/fmadd.d_b15-01.S", //"rv64i_m/D/src/fmsub.d_b15-01.S", From 4877633977320f03003f9e925b9ac607bcdc33cb Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 21 Jun 2024 22:16:09 -0700 Subject: [PATCH 05/10] lint fixes tests vh --- testbench/tests.vh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/testbench/tests.vh b/testbench/tests.vh index 8b3352187..6a78dcd3a 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1802,6 +1802,8 @@ string imperas32f[] = '{ }; + + string arch64d_fma[] = '{ `RISCVARCHTEST, //"rv64i_m/D/src/fmadd.d_b15-01.S", //"rv64i_m/D/src/fmsub.d_b15-01.S", From eeea783da0fc168c144c60cc12ee5a09847a4e35 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 21 Jun 2024 23:15:34 -0700 Subject: [PATCH 06/10] lint --- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index b97056b70..869b06f74 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -45,7 +45,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] FIntDivResultM // U/Q(XLEN.0) ); - logic [P.DIVb+3:0] um, Sum; + logic [P.DIVb+3:0] Sum; logic [P.INTDIVb+3:0] W; logic [P.DIVb:0] PreUmM; logic NegStickyM; From 3618c6c593d4d29db97d48614cd914f9b5c934ca Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 28 Jun 2024 21:19:10 -0700 Subject: [PATCH 07/10] intdivble changes --- src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index 2a43b2d91..8aa9b59c7 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -67,7 +67,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( // Integer div/rem signals logic BZeroM; // Denominator is zero - logic [P.DIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount + logic [P.INTDIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor logic ISpecialCaseE; // Integer div/remainder special cases diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 869b06f74..10d9e038f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -38,7 +38,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( input logic SqrtM, SpecialCaseM, input logic [P.XLEN-1:0] AM, // U/Q(XLEN.0) input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M, - input logic [P.DIVBLEN-1:0] IntNormShiftM, + input logic [P.INTDIVBLEN-1:0] IntNormShiftM, output logic [P.DIVb:0] UmM, // U1.DIVb result significand output logic WZeroE, output logic DivStickyM, diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 737d9089a..cdc076ae4 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -57,7 +57,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( logic [P.NE+1:0] UeE; // Result Exponent (FP only) logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input logic [P.DIVBLEN-1:0] mE, ell; // Leading zeros of inputs - logic [P.DIVBLEN-1:0] IntResultBitsE; // bits in integer result + logic [P.INTDIVBLEN-1:0] IntResultBitsE; // bits in integer result logic AZeroE, BZeroE; // A or B is Zero for integer division logic SignedDivE; // signed division logic AsE, BsE; // Signs of integer inputs @@ -214,7 +214,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( fdivsqrtcycles #(P) cyclecalc(.Nf, .IntDivE, .IntResultBitsE, .CyclesE); if (P.IDIV_ON_FPU) begin:intpipelineregs - logic [P.DIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE; + logic [P.INTDIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE; logic RemOpE; /* verilator lint_off WIDTH */ From 6cb6ff429be6b9e5ee9c1e7e77816f579ca31801 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 28 Jun 2024 21:28:09 -0700 Subject: [PATCH 08/10] Revert "intdivble changes" This reverts commit 3618c6c593d4d29db97d48614cd914f9b5c934ca. --- src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index 8aa9b59c7..2a43b2d91 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -67,7 +67,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( // Integer div/rem signals logic BZeroM; // Denominator is zero - logic [P.INTDIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount + logic [P.DIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor logic ISpecialCaseE; // Integer div/remainder special cases diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 10d9e038f..869b06f74 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -38,7 +38,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( input logic SqrtM, SpecialCaseM, input logic [P.XLEN-1:0] AM, // U/Q(XLEN.0) input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M, - input logic [P.INTDIVBLEN-1:0] IntNormShiftM, + input logic [P.DIVBLEN-1:0] IntNormShiftM, output logic [P.DIVb:0] UmM, // U1.DIVb result significand output logic WZeroE, output logic DivStickyM, diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index cdc076ae4..737d9089a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -57,7 +57,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( logic [P.NE+1:0] UeE; // Result Exponent (FP only) logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input logic [P.DIVBLEN-1:0] mE, ell; // Leading zeros of inputs - logic [P.INTDIVBLEN-1:0] IntResultBitsE; // bits in integer result + logic [P.DIVBLEN-1:0] IntResultBitsE; // bits in integer result logic AZeroE, BZeroE; // A or B is Zero for integer division logic SignedDivE; // signed division logic AsE, BsE; // Signs of integer inputs @@ -214,7 +214,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( fdivsqrtcycles #(P) cyclecalc(.Nf, .IntDivE, .IntResultBitsE, .CyclesE); if (P.IDIV_ON_FPU) begin:intpipelineregs - logic [P.INTDIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE; + logic [P.DIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE; logic RemOpE; /* verilator lint_off WIDTH */ From b04d387e7ca0ae8400c2b1dd169ea21850c3638c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 28 Jun 2024 22:13:35 -0700 Subject: [PATCH 09/10] removed redundant signals --- config/shared/config-shared.vh | 1 - config/shared/parameter-defs.vh | 3 --- src/cvw.sv | 3 --- 3 files changed, 7 deletions(-) diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 08b8ab739..91e1d4100 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -108,7 +108,6 @@ localparam DIVBLEN = $clog2(DIVb+1); // enough bi localparam INTRESBITS = XLEN + LOGR; // number of bits in a result: r integer + XLEN fractional localparam INTFPDUR = (INTRESBITS-1)/RK + 1 ; localparam INTDIVb = INTFPDUR*RK - LOGR; -localparam INTDIVBLEN = $clog2(INTDIVb+1); // largest length in IEU/FPU localparam BASECVTLEN = `max(XLEN, NF); // convert length excluding Zfa fcvtmod.w.d diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index cd2a12564..36482cf4f 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -200,8 +200,5 @@ localparam cvw_t P = '{ DURLEN : DURLEN, DIVb : DIVb, DIVBLEN : DIVBLEN, - INTRESBITS : INTRESBITS, - INTFPDUR : INTFPDUR, INTDIVb : INTDIVb, - INTDIVBLEN : INTDIVBLEN }; diff --git a/src/cvw.sv b/src/cvw.sv index 878f73f57..2e50ca8b9 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -295,10 +295,7 @@ typedef struct packed { int DIVb ; int DIVBLEN ; // integer division/remainder constants - int INTRESBITS ; - int INTFPDUR ; int INTDIVb ; - int INTDIVBLEN ; } cvw_t; From ec4d4e2a8b5d7e54475a4e44c2d447a633afce16 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 30 Jun 2024 19:15:42 -0700 Subject: [PATCH 10/10] param defs lint --- config/shared/parameter-defs.vh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 36482cf4f..c80b00232 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -200,5 +200,6 @@ localparam cvw_t P = '{ DURLEN : DURLEN, DIVb : DIVb, DIVBLEN : DIVBLEN, - INTDIVb : INTDIVb, + INTDIVb : INTDIVb }; +