diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index 736535ce9..02e232bd7 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -39,7 +39,6 @@ module cache #(parameter integer LINELEN,
    input logic				   InvalidateCacheM,
    input logic [11:0]		   NextAdr, // virtual address, but we only use the lower 12 bits.
    input logic [`PA_BITS-1:0]  PAdr, // physical address
-   input logic [11:0]		   NoTranAdr, // physical or virtual address   
    input logic [`XLEN-1:0]	   FinalWriteData,
    output logic [`XLEN-1:0]	   ReadDataWord,
    output logic				   CacheCommitted,
@@ -120,7 +119,7 @@ module cache #(parameter integer LINELEN,
 
   mux3 #(INDEXLEN)
   AdrSelMux(.d0(NextAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
-			.d1(NoTranAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+			.d1(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 			.d2(FlushAdr),
 			.s(SelAdr),
 			.y(RAdr));
@@ -147,7 +146,7 @@ module cache #(parameter integer LINELEN,
     cachereplacementpolicy(.clk, .reset,
               .WayHit,
               .VictimWay,
-              .PAdr(NoTranAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+              .PAdr(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
               .RAdr,
               .LRUWriteEn);
   end else begin:vict
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index f68bceef2..3067f82d0 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -269,7 +269,6 @@ module ifu (
 			 .FlushCache(1'b0),
 			 .NextAdr(PCNextFMux),
 			 .PAdr(PCPF),
-			 .NoTranAdr(PCFMux[11:0]),
 			 .CacheCommitted(),
 			 .InvalidateCacheM(InvalidateICacheM));
 
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index bb664dfaf..1dc2be24a 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -98,6 +98,7 @@ module lsu
   logic [1:0] 				   LSURWM;
   logic [1:0] 				   PreLSURWM;
   logic [2:0] 				   LSUFunct3M;
+  logic [6:0] 				   LSUFunct7M;
   logic [1:0] 				   LSUAtomicM;
 (* mark_debug = "true" *)  logic [`PA_BITS-1:0] 		   PreLSUPAdrM, LocalLSUBusAdr;
   logic [11:0] 				   PreLSUAdrE, LSUAdrE;  
@@ -146,6 +147,7 @@ module lsu
     // multiplex the outputs to LSU
     mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLSURWM);
     mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
+    mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);    
     mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
     mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE);
     mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM);
@@ -179,6 +181,7 @@ module lsu
     
     assign PreLSURWM = MemRWM;
     assign LSUFunct3M = Funct3M;
+    assign LSUFunct7M = Funct7M;
     assign LSUAtomicM = AtomicM;
     assign PreLSUAdrE = IEUAdrE[11:0];
     assign PreLSUPAdrM = IEUAdrExtM;
@@ -301,7 +304,7 @@ module lsu
 			.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) 
 	 dcache(.clk, .reset, .CPUBusy,
 			.RW(CacheableM ? LSURWM : 2'b00), .FlushCache(FlushDCacheM), .Atomic(CacheableM ? LSUAtomicM : 2'b00), 
-			.NextAdr(LSUAdrE), .PAdr(LSUPAdrM), .NoTranAdr(PreLSUPAdrM[11:0]),
+			.NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
 			.FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM), .CacheStall(DCacheStall),
 			.CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), 
 			.IgnoreRequest, .CacheCommitted(DCacheCommittedM),
@@ -336,7 +339,7 @@ module lsu
 
   if (`A_SUPPORTED) begin : amo
     logic [`XLEN-1:0] AMOResult;
-    amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(LSUFunct3M[1:0]), 
+    amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), 
                   .result(AMOResult));
     mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
   end else
diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv
index e69028118..dd206996b 100644
--- a/pipelined/src/mmu/mmu.sv
+++ b/pipelined/src/mmu/mmu.sv
@@ -111,7 +111,12 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
   end
 
   // If translation is occuring, select translated physical address from TLB
-  mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);
+  // the lower 12 bits are the page offset. These are never changed from the orginal
+  // non translated address.
+  //mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);
+  mux2 #(`PA_BITS-12) addressmux(PAdr[`PA_BITS-1:12], TLBPAdr[`PA_BITS-1:12], Translate, PhysicalAddress[`PA_BITS-1:12]);
+  assign PhysicalAddress[11:0] = PAdr[11:0];
+  
   
   ///////////////////////////////////////////
   // Check physical memory accesses