From 847c7930c4ca548bcc5edaf0309b11a890f1438c Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 26 May 2022 16:29:13 -0700 Subject: [PATCH] added LSUBurstDone signal to signal when a burst has finished --- pipelined/src/ebu/ahblite.sv | 7 ++++++- pipelined/src/ifu/ifu.sv | 3 ++- pipelined/src/lsu/busdp.sv | 11 ++--------- pipelined/src/lsu/busfsm.sv | 14 ++++++++++++++ pipelined/src/lsu/lsu.sv | 3 ++- pipelined/src/wally/wallypipelinedcore.sv | 9 ++++++--- 6 files changed, 32 insertions(+), 15 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 690d998ac..2c61a1c61 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -46,6 +46,7 @@ module ahblite ( output logic [`XLEN-1:0] IFUBusHRDATA, output logic IFUBusAck, input logic [2:0] IFUBurstType, + input logic IFUBurstDone, // Signals from Data Cache input logic [`PA_BITS-1:0] LSUBusAdr, input logic LSUBusRead, @@ -54,6 +55,7 @@ module ahblite ( output logic [`XLEN-1:0] LSUBusHRDATA, input logic [2:0] LSUBusSize, input logic [2:0] LSUBurstType, + input logic LSUBurstDone, output logic LSUBusAck, // AHB-Lite external signals (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, @@ -89,6 +91,9 @@ module ahblite ( // Data accesses have priority over instructions. However, if a data access comes // while an instruction read is occuring, the instruction read finishes before // the data access can take place. + // *** This is no longer true when adding burst mode. We need to finish the current + // read before doing another read. Need to work this out, but preliminarily we can + // store the current read type in a flop and use that to figure out what burst type to use. flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); @@ -124,7 +129,7 @@ module ahblite ( assign #1 HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; - assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH + assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. 000: Single (SINGLE) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 66f4acfdd..abd4ea2e9 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -42,6 +42,7 @@ module ifu ( (* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic [2:0] IFUBurstType, +(* mark_debug = "true" *) output logic IFUBurstDone, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute output logic [`XLEN-1:0] PCLinkE, @@ -191,7 +192,7 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(.clk, .reset, .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(), - .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), + .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUBurstDone(IFUBurstDone), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .WordCount(), .DCacheFetchLine(ICacheFetchLine), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 7b837cea1..f2666cd5d 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -44,6 +44,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic LSUBusRead, output logic [2:0] LSUBusSize, output logic [2:0] LSUBurstType, + output logic LSUBurstDone, input logic [2:0] LSUFunct3M, output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. output logic [LOGWPL-1:0] WordCount, @@ -68,14 +69,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalLSUBusAdr; - always_comb begin - case(WORDSPERLINE) - 4: LSUBurstType = 3'b010; // WRAP4 - 8: LSUBurstType = 3'b100; // WRAP8 - 16: LSUBurstType = 3'b110; // WRAP16 - default: LSUBurstType = 3'b000; // No Burst - endcase - end // *** implement flops as an array if feasbile; DCacheBusWriteData might be a problem // *** better name than DCacheBusWriteData @@ -94,5 +87,5 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, - .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); + .LSUBurstType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index f3860c0d6..cbafdb184 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -48,6 +48,8 @@ module busfsm #(parameter integer WordCountThreshold, output logic LSUBusWrite, output logic LSUBusWriteCrit, output logic LSUBusRead, + output logic [2:0] LSUBurstType, + output logic LSUBurstDone, output logic DCacheBusAck, output logic BusCommittedM, output logic SelUncachedAdr, @@ -62,6 +64,7 @@ module busfsm #(parameter integer WordCountThreshold, logic WordCountFlag; logic [LOGWPL-1:0] NextWordCount; logic UnCachedAccess; + logic [2:0] LocalBurstType; typedef enum logic [2:0] {STATE_BUS_READY, @@ -120,6 +123,17 @@ module busfsm #(parameter integer WordCountThreshold, endcase end + always_comb begin + case(WordCountThreshold) + 4: LSUBurstType = 3'b010; // WRAP4 + 8: LSUBurstType = 3'b100; // WRAP8 + 16: LSUBurstType = 3'b110; // WRAP16 + default: LSUBurstType = 3'b000; // No Burst + endcase // This block might be better in the FSM. WordCountThreshold is WordsPerLine + end + + assign LSUBurstType = (UnCachedAccess) ? LocalBurstType : '0; // Don't want to use burst when doing an Uncached Access + assign LSUBurstDone = WordCountFlag; assign CntReset = BusCurrState == STATE_BUS_READY; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 84a92872a..3afabe439 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -70,6 +70,7 @@ module lsu ( (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, (* mark_debug = "true" *) output logic [2:0] LSUBusSize, (* mark_debug = "true" *) output logic [2:0] LSUBurstType, + (* mark_debug = "true" *) output logic LSUBurstDone, // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -212,7 +213,7 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( .clk, .reset, - .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, + .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUBurstDone, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 21f9dcc58..557811d34 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -137,6 +137,7 @@ module wallypipelinedcore ( logic IFUBusRead; logic IFUBusAck; logic [2:0] IFUBurstType; + logic IFUBurstDone; // AHB LSU interface logic [`PA_BITS-1:0] LSUBusAdr; @@ -155,6 +156,7 @@ module wallypipelinedcore ( logic InstrAccessFaultF; logic [2:0] LSUBusSize; logic [2:0] LSUBurstType; + logic LSUBurstDone; logic DCacheMiss; logic DCacheAccess; @@ -170,7 +172,7 @@ module wallypipelinedcore ( .FlushF, .FlushD, .FlushE, .FlushM, // Fetch .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, - .IFUBusRead, .IFUStallF, .IFUBurstType, + .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUBurstDone, .ICacheAccess, .ICacheMiss, // Execute @@ -251,7 +253,7 @@ module wallypipelinedcore ( .ReadDataM, .FlushDCacheM, // connected to ahb (all stay the same) .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, + .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUBurstDone, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -283,12 +285,13 @@ module wallypipelinedcore ( .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), .IFUBusAdr, - .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, + .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, .IFUBurstDone, // Signals from Data Cache .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, .LSUBusHRDATA, .LSUBusSize, .LSUBurstType, + .LSUBurstDone, .LSUBusAck, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,