From 84116a756ef5363b3edea40b3b1ad45845e0f7d9 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 29 Nov 2021 17:43:47 -0600
Subject: [PATCH] Added final IP generator script (proc_sys_reset).

---
 fpga/generator/proc_sys_reset.tcl | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 fpga/generator/proc_sys_reset.tcl

diff --git a/fpga/generator/proc_sys_reset.tcl b/fpga/generator/proc_sys_reset.tcl
new file mode 100644
index 000000000..61a5655c9
--- /dev/null
+++ b/fpga/generator/proc_sys_reset.tcl
@@ -0,0 +1,24 @@
+
+#set partNumber $::env(XILINX_PART)
+#set boardNmae $::env(XILINX_BOARD)
+set partNumber xcvu9p-flga2104-2L-e
+set boardName  xilinx.com:vcu118:part0:2.4
+
+set ipName xlnx_proc_sys_reset
+
+create_project $ipName . -force -part $partNumber
+set_property board_part $boardName [current_project]
+
+# really just these two lines which change
+create_ip -name proc_sys_reset -vendor xilinx.com -library ip -module_name $ipName
+set_property -dict [list CONFIG.C_AUX_RESET_HIGH {1} \
+			CONFIG.C_AUX_RST_WIDTH {1} \
+			CONFIG.C_EXT_RESET_HIGH {1} \
+			CONFIG.C_EXT_RST_WIDTH {1} \
+			CONFIG.C_NUM_BUS_RST {1}] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1