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https://github.com/openhwgroup/cvw
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Working first cut of the cache changes moving the replay to a save/restore.
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
This commit is contained in:
Ross Thompson
parent
c3122ce214
commit
83fdedcec6
5
pipelined/src/cache/cache.sv
vendored
5
pipelined/src/cache/cache.sv
vendored
@ -106,6 +106,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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logic [NUMWAYS-1:0] VDWriteEnableWay;
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logic SelFlush;
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logic ResetOrFlushAdr, ResetOrFlushWay;
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logic save, restore;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Read Path
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@ -125,7 +126,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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.WriteWordEnable(SRAMWordEnable),
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.TagWriteEnable(SRAMLineWayWriteEnable),
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.WriteData(SRAMWriteData),
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.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .Victim(VictimWay), .Flush(FlushWay), .SelFlush,
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.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .Victim(VictimWay), .Flush(FlushWay),
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.save, .restore, .SelFlush,
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.SelectedReadDataLine(ReadDataLineWay), .WayHit, .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay),
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.InvalidateAll(InvalidateCacheM));
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if(NUMWAYS > 1) begin:vict
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@ -213,5 +215,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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.SRAMLineWriteEnable, .SelEvict, .SelFlush,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
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.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
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.save, .restore,
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.VDWriteEnable, .LRUWriteEn);
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endmodule
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25
pipelined/src/cache/cachefsm.sv
vendored
25
pipelined/src/cache/cachefsm.sv
vendored
@ -74,6 +74,8 @@ module cachefsm
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output logic FlushWayCntEn,
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output logic FlushAdrCntRst,
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output logic FlushWayCntRst,
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output logic save,
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output logic restore,
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output logic VDWriteEnable
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);
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@ -141,7 +143,8 @@ module cachefsm
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NextState = STATE_READY;
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CacheFetchLine = 1'b0;
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CacheWriteLine = 1'b0;
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save = 1'b0;
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restore = 1'b0;
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case (CurrState)
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STATE_READY: begin
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@ -178,7 +181,8 @@ module cachefsm
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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PreSelAdr = 2'b01;
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//PreSelAdr = 2'b01;
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save = 1'b1;
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end
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else begin
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SRAMWordWriteEnable = 1'b1;
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@ -194,7 +198,8 @@ module cachefsm
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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PreSelAdr = 2'b01;
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//PreSelAdr = 2'b01;
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save = 1'b1;
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end
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else begin
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NextState = STATE_READY;
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@ -210,7 +215,8 @@ module cachefsm
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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PreSelAdr = 2'b01;
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//PreSelAdr = 2'b01;
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save = 1'b1;
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end
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else begin
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NextState = STATE_READY;
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@ -278,6 +284,7 @@ module cachefsm
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PreSelAdr = 2'b01;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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save = 1'b1;
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end
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else begin
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SRAMWordWriteEnable = 1'b1;
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@ -289,7 +296,8 @@ module cachefsm
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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PreSelAdr = 2'b01;
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//PreSelAdr = 2'b01;
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save = 1'b1;
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end
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else begin
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NextState = STATE_READY;
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@ -304,7 +312,8 @@ module cachefsm
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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PreSelAdr = 2'b01;
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//PreSelAdr = 2'b01;
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save = 1'b1;
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end
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else begin
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NextState = STATE_READY;
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@ -325,9 +334,10 @@ module cachefsm
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STATE_CPU_BUSY: begin
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PreSelAdr = 2'b00;
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restore = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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PreSelAdr = 2'b01;
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//PreSelAdr = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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@ -339,6 +349,7 @@ module cachefsm
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SRAMWordWriteEnable = 1'b0;
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SetDirty = 1'b0;
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LRUWriteEn = 1'b0;
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restore = 1'b1;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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end
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27
pipelined/src/cache/cacheway.sv
vendored
27
pipelined/src/cache/cacheway.sv
vendored
@ -51,6 +51,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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input logic InvalidateAll,
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input logic SelFlush,
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input logic Flush,
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input logic save, restore,
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output logic [LINELEN-1:0] SelectedReadDataLine,
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output logic WayHit,
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@ -59,10 +60,10 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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logic [NUMLINES-1:0] ValidBits;
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logic [NUMLINES-1:0] DirtyBits;
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logic [LINELEN-1:0] ReadDataLine;
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logic [TAGLEN-1:0] ReadTag;
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logic Valid;
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logic Dirty;
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logic [LINELEN-1:0] ReadDataLine, ReadDataLineRaw, ReadDataLineSaved;
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logic [TAGLEN-1:0] ReadTag, ReadTagRaw, ReadTagSaved;
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logic Valid, ValidRaw, ValidSaved;
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logic Dirty, DirtyRaw, DirtySaved;
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logic SelData;
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logic SelTag;
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@ -76,7 +77,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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/////////////////////////////////////////////////////////////////////////////////////////////
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sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk),
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.Adr(RAdr), .ReadData(ReadTag),
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.Adr(RAdr), .ReadData(ReadTagRaw),
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.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable));
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// AND portion of distributed tag multiplexer
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@ -92,7 +93,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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genvar words;
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for(words = 0; words < LINELEN/`XLEN; words++) begin: word
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sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr),
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.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
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.ReadData(ReadDataLineRaw[(words+1)*`XLEN-1:words*`XLEN] ),
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.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
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.WriteEnable(WriteEnable & WriteWordEnable[words]));
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end
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@ -115,7 +116,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
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flop #(4) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable, VDWriteEnable},
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{SetValidD, ClearValidD, WriteEnableD, VDWriteEnableD});
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assign Valid = ValidBits[RAdrD];
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assign ValidRaw = ValidBits[RAdrD];
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Dirty Bits
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@ -129,8 +130,18 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= #1 1'b0;
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end
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flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
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assign Dirty = DirtyBits[RAdrD];
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assign DirtyRaw = DirtyBits[RAdrD];
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flopenr #(1) cachedirtysavereg(clk, reset, save, DirtyRaw, DirtySaved);
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mux2 #(1) saverestoredirtymux(DirtyRaw, DirtySaved, restore, Dirty);
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end else assign Dirty = 1'b0;
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// save restore option of handling cpu busy
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flopen #(TAGLEN+LINELEN) cachereadsavereg(clk, save, {ReadTagRaw, ReadDataLineRaw}, {ReadTagSaved, ReadDataLineSaved});
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flopenr #(1) cachevalidsavereg(clk, reset, save, ValidRaw, ValidSaved);
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mux2 #(1+TAGLEN+LINELEN) saverestoremux({ValidRaw, ReadTagRaw, ReadDataLineRaw}, {ValidSaved, ReadTagSaved, ReadDataLineSaved},
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restore, {Valid, ReadTag, ReadDataLine});
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endmodule
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