From 83df3dfe83e860aa272294032725383923158801 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 15 Jan 2024 16:02:37 -0600
Subject: [PATCH] Fixed the zifencei bug (part of issue 405).

---
 src/ieu/controller.sv | 2 +-
 src/lsu/lsu.sv        | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 3507ec3e9..e5cfff9ed 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -370,7 +370,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   // Fences
   // Ordinary fence is presently a nop
   // fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
-  if (P.ZIFENCEI_SUPPORTED & P.ICACHE_SUPPORTED) begin:fencei
+  if (P.ZIFENCEI_SUPPORTED & (P.ICACHE_SUPPORTED | P.DCACHE_SUPPORTED)) begin:fencei
     logic FenceID;
     assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
     assign InvalidateICacheD = FenceID;
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index e7d6707d6..06d64c154 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -342,7 +342,6 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       assign DCacheStallM = CacheStall & ~IgnoreRequestTLB;
       assign CacheBusRW = CacheBusRWTemp;
 
-      // *** add support for cboz
       ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN),  .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
         .HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB),
         .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),