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priviledge .* fixed, passed local regression

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kwan 2021-12-13 00:22:01 -08:00
parent 96ac298596
commit 83dae9d774
1 changed files with 8 additions and 8 deletions
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16
wally-pipelined/src/privileged/privileged.sv
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@ -147,7 +147,7 @@ module privileged (
/////////////////////////////////////////// ///////////////////////////////////////////
//privdec pmd(.InstrM(InstrM[31:20]),.*);
privdec pmd(.InstrM(InstrM[31:20]), privdec pmd(.InstrM(InstrM[31:20]),
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
.PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM,
@ -156,8 +156,8 @@ module privileged (
/////////////////////////////////////////// ///////////////////////////////////////////
// Control and Status Registers // Control and Status Registers
/////////////////////////////////////////// ///////////////////////////////////////////
//csr csr(.*);
csr csr(.clk,. reset, csr csr(.clk, .reset,
.FlushE, .FlushM, .FlushW, .FlushE, .FlushM, .FlushW,
.StallE, .StallM, .StallW, .StallE, .StallM, .StallW,
.InstrM, .PCM, .SrcAM, .InstrM, .PCM, .SrcAM,
@ -171,9 +171,9 @@ module privileged (
.CauseM, .NextFaultMtvalM, .STATUS_MPP, .CauseM, .NextFaultMtvalM, .STATUS_MPP,
.STATUS_SPP, .STATUS_TSR, .STATUS_SPP, .STATUS_TSR,
.MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
.MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, .MEDELEG_REGW, .MIDELEG_REGW, .SEDELEG_REGW, .SIDELEG_REGW,
.SATP_REGW, .SATP_REGW,
.MIP_REGW, .MIE_REGW, .SIP_REGW, S.IE_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
.STATUS_MIE, .STATUS_SIE, .STATUS_MIE, .STATUS_SIE,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW,
.PMPCFG_ARRAY_REGW, .PMPCFG_ARRAY_REGW,
@ -219,17 +219,17 @@ module privileged (
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
// *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021 // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
//trap trap(.*);
trap trap(.clk, .reset, trap trap(.clk, .reset,
.InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM, .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
.LoadAccessFaultM, .StoreAccessFaultM, .EcallFaultM, .InstrPageFaultM, .LoadAccessFaultM, .StoreAccessFaultM, .EcallFaultM, .InstrPageFaultM,
.LoadPageFaultM, .StorePageFaultM, .LoadPageFaultM, .StorePageFaultM,
.mretM, .sretM, .uretM, .mretM, .sretM, .uretM,
.PrivilegeModeW, .NextPrivilegeModeM .PrivilegeModeW, .NextPrivilegeModeM,
.MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
.STATUS_MIE, .STATUS_SIE .STATUS_MIE, .STATUS_SIE,
.PCM, .PCM,
.InstrMisalignedAdrM, .MemAdrM, .InstrMisalignedAdrM, .MemAdrM,
.InstrM, .InstrM,