diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/cacheway.sv
similarity index 98%
rename from wally-pipelined/src/cache/DCacheMem.sv
rename to wally-pipelined/src/cache/cacheway.sv
index 207a0aa40..288d8fc00 100644
--- a/wally-pipelined/src/cache/DCacheMem.sv
+++ b/wally-pipelined/src/cache/cacheway.sv
@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
+module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
 		   parameter OFFSETLEN, parameter INDEXLEN) 
   (input logic 		       clk,
    input logic 				       reset,
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 0d65c9a2c..b2e4cdd75 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -202,10 +202,9 @@ module dcache
   assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW;
   
 
-  DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), 
-	      .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
-  MemWay[NUMWAYS-1:0](.clk(clk),
-	 .reset(reset),
+  cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
+  MemWay[NUMWAYS-1:0](.clk,
+	 .reset,
 	 .Adr(SRAMAdr),
 	 .MemPAdrM(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
 	 .WriteEnable(SRAMWayWriteEnable),
@@ -218,11 +217,11 @@ module dcache
 	 .SetDirty(SetDirtyM),
 	 .ClearDirty(ClearDirtyM),
 	 .SelEvict,
-	 .VictimWay(VictimWay),
-	 .ReadDataBlockWayMaskedM(ReadDataBlockWayMaskedM),
-	 .WayHit(WayHit),
-	 .VictimDirtyWay(VictimDirtyWay),
-	 .VictimTagWay(VictimTagWay));
+	 .VictimWay,
+	 .ReadDataBlockWayMaskedM,
+	 .WayHit,
+	 .VictimDirtyWay,
+	 .VictimTagWay);
 
   always_ff @(posedge clk, posedge reset) begin
     if (reset) begin