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https://github.com/openhwgroup/cvw
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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commit
83a76ffb0c
10
README.md
10
README.md
@ -18,8 +18,16 @@ mkdir build
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cd build
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cd build
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set RISCV=/cad/riscv/gcc/bin (or whatever your path is)
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set RISCV=/cad/riscv/gcc/bin (or whatever your path is)
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../configure --prefix=$RISCV
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../configure --prefix=$RISCV
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make
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make (this will take a while to build SPIKE)
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sudo make install
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sudo make install
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cd ../../riscv-arch-test
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cp ../riscv-isa-sim/arch_test_target/spike/Makefile.include .
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edit Makefile.include
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change line with TARGETDIR to /home/harris/test/riscv-wally/addins/riscv-isa-sim/arch_test_target (or whatever your path is) ***fix
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add line export RISCV_PREFIX = riscv64-unknown-elf- # this might not be needed if you have 32-bit versions of the riscv gcc compiler built separately
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make
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make XLEN=32
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exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim
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```
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```
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Notes:
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Notes:
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