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https://github.com/openhwgroup/cvw
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Progress towards unified regression.
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3fdfa0f705
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@ -265,7 +265,7 @@ module testbench;
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logic ResetCntRst;
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logic ResetCntRst;
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logic CopyRAM;
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logic CopyRAM;
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string signame, memfilename, bootmemfilename, uartoutfilename, pathname;
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string signame, elffilename, memfilename, bootmemfilename, uartoutfilename, pathname;
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integer begin_signature_addr, end_signature_addr, signature_size;
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integer begin_signature_addr, end_signature_addr, signature_size;
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integer uartoutfile;
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integer uartoutfile;
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@ -366,20 +366,24 @@ module testbench;
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if(SelectTest) begin
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if(SelectTest) begin
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if (riscofTest) begin
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if (riscofTest) begin
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memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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elffilename = {pathname, tests[test], "ref/ref.elf"};
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ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
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ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
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ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
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end else if(TEST == "buildroot") begin
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end else if(TEST == "buildroot") begin
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memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
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memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
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elffilename = "buildroot";
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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uartoutfilename = {"logs/", TEST, "_uart.out"};
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uartoutfilename = {"logs/", TEST, "_uart.out"};
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uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file
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uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file
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ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
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ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
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ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
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ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
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end else if(ElfFile != "none") begin
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end else if(ElfFile != "none") begin
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elffilename = ElfFile;
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memfilename = {ElfFile, ".memfile"};
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memfilename = {ElfFile, ".memfile"};
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ProgramAddrMapFile = {ElfFile, ".objdump.addr"};
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ProgramAddrMapFile = {ElfFile, ".objdump.addr"};
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ProgramLabelMapFile = {ElfFile, ".objdump.lab"};
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ProgramLabelMapFile = {ElfFile, ".objdump.lab"};
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end else begin
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end else begin
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elffilename = {pathname, tests[test], ".elf"};
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memfilename = {pathname, tests[test], ".elf.memfile"};
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memfilename = {pathname, tests[test], ".elf.memfile"};
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ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
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ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
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ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
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@ -421,7 +425,7 @@ module testbench;
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end else if (TEST == "coverage64gc") begin
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end else if (TEST == "coverage64gc") begin
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$display("Coverage tests don't get checked");
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$display("Coverage tests don't get checked");
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end else if (ElfFile != "none") begin
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end else if (ElfFile != "none") begin
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$display("Single Elf file tests don't get signatured checked.");
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$display("Single Elf file tests are not signatured verified.");
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`ifdef VERILATOR // this macro is defined when verilator is used
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`ifdef VERILATOR // this macro is defined when verilator is used
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$finish; // Simulator Verilator needs $finish to terminate simulation.
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$finish; // Simulator Verilator needs $finish to terminate simulation.
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`elsif SIM_VCS // this macro is defined when vcs is used
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`elsif SIM_VCS // this macro is defined when vcs is used
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@ -688,6 +692,7 @@ end
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.CMP_CSR (1)
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.CMP_CSR (1)
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) idv_trace2api(rvvi);
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) idv_trace2api(rvvi);
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string filename;
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initial begin
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initial begin
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int iter;
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int iter;
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#1;
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#1;
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@ -705,7 +710,10 @@ end
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void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56));
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void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56));
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void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
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void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
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if (!rvviRefInit("")) begin
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if(elffilename == "buildroot") filename = "";
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else filename = elffilename;
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if (!rvviRefInit(filename)) begin
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$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
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$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
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$fatal;
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$fatal;
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end
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end
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