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https://github.com/openhwgroup/cvw
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Added files to repo
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parent
2519d7705b
commit
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1
.gitignore
vendored
1
.gitignore
vendored
@ -21,6 +21,7 @@ wlft*
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/imperas-riscv-tests/logs
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/imperas-riscv-tests/logs
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*.o
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*.o
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*.d
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*.d
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*.vstf
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testsBP/*/*/*.elf*
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testsBP/*/*/*.elf*
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testsBP/*/OBJ/*
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testsBP/*/OBJ/*
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testsBP/*/*.a
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testsBP/*/*.a
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35
Makefile
35
Makefile
@ -1,31 +1,18 @@
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#make all: submodules other
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#make all: submodules other
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#submodules: addins/riscv-isa-sim addins/riscv-arch-test
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# git pull --recurse-submodules
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#
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#other:
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make all:
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make all:
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# move these parts into compiling archtest separtately
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# move these parts into compiling archtest separtately
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cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F
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# cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F
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cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D
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# cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D
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<<<<<<< HEAD
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# sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include
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#why cat
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# sed -i 's/--isa=rv64i /--isa=64id/' addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include
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cat addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include
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# if [ -d "addins/riscv-isa-sim/build" ]; then echo "Build exists"; else mkdir addins/riscv-isa-sim/build; fi
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=======
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# cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin
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>>>>>>> 29f2a1c5479d7a80debdb1ac337fcda628cc57a3
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# make -C addins/riscv-isa-sim/build
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sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include
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# sudo make install -C addins/riscv-isa-sim/build
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sed -i 's/--isa=rv64i /--isa=64if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include
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# cp addins/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
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if [ -d "addins/riscv-isa-sim/build" ]; then echo "Build exists"; else mkdir addins/riscv-isa-sim/build; fi
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cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin
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make -C addins/riscv-isa-sim/build
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# does sudo work?
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sudo make install -C addins/riscv-isa-sim/build
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cp addins/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
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# update with path including $RISCV_TOOLS
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# update with path including $RISCV_TOOLS
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# separate into make tests and make regression
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# separate into make tests and make regression
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sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include
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cp $RISCV/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
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sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= $RISCV/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include
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echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include
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echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include
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make -C addins/riscv-arch-test
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make -C addins/riscv-arch-test
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make -C addins/riscv-arch-test XLEN=32
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make -C addins/riscv-arch-test XLEN=32
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50
wally-pipelined/README.txt
Normal file
50
wally-pipelined/README.txt
Normal file
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Code Improvements
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David_Harris@hmc.edu 15 Nov 2021
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Remove depricated N-Mode stuff, including sd in privileged.sv
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Look at version 13? of privileged spec. What should we add?
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Reduce size of repo
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Timing optimization (Kip, Shreya)
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Use ForwardSrcA instead of SrcA for mdu / fpu
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Look at TLB -> PMP -> Access Fault -> Trap
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may be able to precompute
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Try flattening, see speedup
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Take out Mul synthesis modes
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RISCV-Arch-tests
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Port MMU tests
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FPU
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spec difference on signaling/quiet NAN propagation
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SRT Div/Sqrt (Katherine, maybe Udeema)
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Get riscv-arch-tests running (James, Katherine)
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Get testfloat all passing
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Katherine's FPU optimization
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Linux Boot
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Ben, Skyler
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FPGA Boot Linux (Ross)
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IFU/LSU
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Block diagrams, code cleanup
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Burst mode transfers to speed up IPC
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Implications of no byte enables on subword write - do stores take extra cycle, should this be avoided?
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28 nm Implementation
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Install processor
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Memory macros
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Synthesis & PNR
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Timing review
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Benchmarking
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Flow
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Kevin Kim has a makefile to check out and build all the pieces. Make sure this is running; change Repo README to use his makefile
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Code cleanup
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.* fixes by thanksgiving
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Rename top-level modules to abbreviations
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Rename muldiv to mdu
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Get rid of DESIGN_COMPILER flag and redundant multiplier
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1
wally-pipelined/linux-testgen/linux-testvectors/all.txt
Symbolic link
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wally-pipelined/linux-testgen/linux-testvectors/all.txt
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/courses/e190ax/buildroot_boot/all.txt
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1
wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt
Symbolic link
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wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt
Symbolic link
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/courses/e190ax/buildroot_boot/bootmem.txt
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/courses/e190ax/buildroot_boot/checkpoint8500000
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1
wally-pipelined/linux-testgen/linux-testvectors/ram.txt
Symbolic link
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wally-pipelined/linux-testgen/linux-testvectors/ram.txt
Symbolic link
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/courses/e190ax/buildroot_boot/ram.txt
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1
wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump
Symbolic link
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wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump
Symbolic link
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/courses/e190ax/buildroot_boot/vmlinux.objdump
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/courses/e190ax/buildroot_boot/vmlinux.objdump.addr
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/courses/e190ax/buildroot_boot/vmlinux.objdump.lab
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BIN
wally-pipelined/srt/sqrttestgen
Executable file
BIN
wally-pipelined/srt/sqrttestgen
Executable file
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BIN
wally-pipelined/srt/testgen
Executable file
BIN
wally-pipelined/srt/testgen
Executable file
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wally-setup.sh
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wally-setup.sh
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#!/bin/bash
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# wally-setup.sh
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# David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
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# Set up tools for riscv-wally
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echo "Executing wally-setup.sh"
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# Path to RISC-V Tools
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export RISCV=/opt/riscv # change this if you installed the tools in a different location
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# Tools
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export PATH=$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin:$PATH # GCC tools
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export PATH=~/riscv-wally/bin:$PATH # exe2memfile; change this if riscv-wally isn't at your home directory
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export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim
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export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
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export LD_LIBRARY_PATH=$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib:$LD_LIBRARY_PATH
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export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # *** is this the right license server now
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# Imperas; *** remove if not using
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PATH=/cad/riscv/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:/cad/riscv/imperas-riscv-tests/riscv-ovpsim/bin/Liux64:$PATH # *** maybe take this out based on Imperas
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export LD_LIBRARY_PATH=/cad/imperas/Imperas.20200630/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
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IMPERAS_HOME=/cad/imperas/Imperas.20200630
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source $IMPERAS_HOME/bin/setup.sh
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setupImperas $IMPERAS_HOME
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