Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.

pipelined/src/cache/cacheway.sv

@@ -55,9 +55,11 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   output logic                       VictimDirtyWay,
   output logic [TAGLEN-1:0]          VictimTagWay);
 
-  localparam                         WORDSPERLINE = LINELEN/`XLEN;
+  localparam integer                 WORDSPERLINE = LINELEN/`XLEN;
+  localparam integer                 BYTESPERLINE = LINELEN/8;
   localparam                         LOGWPL = $clog2(WORDSPERLINE);
   localparam                         LOGXLENBYTES = $clog2(`XLEN/8);
+  localparam integer                 BYTESPERWORD = `XLEN/8;
 
   logic [NUMLINES-1:0]               ValidBits;
   logic [NUMLINES-1:0]               DirtyBits;
@@ -69,7 +71,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   logic                              SelTag;
   logic [$clog2(NUMLINES)-1:0]       RAdrD;
   logic [2**LOGWPL-1:0]              MemPAdrDecoded;
-  logic [LINELEN/`XLEN-1:0]          SelectedWriteWordEn;
+  logic [WORDSPERLINE-1:0]          SelectedWriteWordEn;
   logic [(`XLEN-1)/8:0]              FinalByteMask;
   
   /////////////////////////////////////////////////////////////////////////////////////////////
@@ -107,12 +109,28 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
 
   // *** instantiate one larger RAM, not one per RAM.  Expand byte mask
   genvar 							  words;
-  for(words = 0; words < LINELEN/`XLEN; words++) begin: word
+  logic [BYTESPERLINE-1:0]     ReplicatedByteMask, SRAMLineByteMask, WordByteEnabled;
+  assign ReplicatedByteMask = {{WORDSPERLINE}{FinalByteMask}};
+  for(words = 0; words < WORDSPERLINE; words++)
+    assign WordByteEnabled[BYTESPERWORD*(words+1)-1:BYTESPERWORD*(words)] = {{BYTESPERWORD}{SelectedWriteWordEn[words]}};
+  assign SRAMLineByteMask = ReplicatedByteMask & WordByteEnabled;
+
+  for(words = 0; words < 1; words++) begin: word
+    sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(LINELEN)) CacheDataMem(.clk, .Adr(RAdr),
+      .ReadData(ReadDataLine),
+      .CacheWriteData(CacheWriteData),
+      .WriteEnable(1'b1), .ByteMask(SRAMLineByteMask));
+  end
+  
+
+/* -----\/----- EXCLUDED -----\/-----
+  for(words = 0; words < WORDSPERLINE; words++) begin: word
     sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr),
       .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
       .CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]),
       .WriteEnable(SelectedWriteWordEn[words]), .ByteMask(FinalByteMask));
   end
+ -----/\----- EXCLUDED -----/\----- */
 
   // AND portion of distributed read multiplexers
   mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);

pipelined/testbench/testbench.sv

@@ -429,6 +429,8 @@ module DCacheFlushFSM
 	  localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
 	  localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
 	  localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+	  localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;      
+	  localparam integer cachenumwords = 1; //testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN;
 	  localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN;        
 	  localparam integer lognumlines = $clog2(numlines);
 	  localparam integer loglinebytelen = $clog2(linebytelen);
@@ -438,16 +440,17 @@ module DCacheFlushFSM
 
 
 	  genvar 			 index, way, cacheWord;
-	  logic [`XLEN-1:0]  CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
+	  logic [linelen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
-	  logic [`XLEN-1:0]  CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
+      logic [linelen-1:0] cacheline;
-	  logic 			 CacheValid  [numways-1:0] [numlines-1:0] [numwords-1:0];
+	  logic [`XLEN-1:0]  CacheTag [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
-	  logic 			 CacheDirty  [numways-1:0] [numlines-1:0] [numwords-1:0];
+	  logic 			 CacheValid  [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
-	  logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
+	  logic 			 CacheDirty  [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
+	  logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
     for(index = 0; index < numlines; index++) begin
 		  for(way = 0; way < numways; way++) begin
-		    for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
+		    for(cacheWord = 0; cacheWord < cachenumwords; cacheWord++) begin
 			    copyShadow #(.tagstart(tagstart),
-					.loglinebytelen(loglinebytelen))
+					.loglinebytelen(loglinebytelen), .linelen(linelen))
 			    copyShadow(.clk,
           .start,
           .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]),
@@ -472,9 +475,14 @@ module DCacheFlushFSM
         #1
         for(i = 0; i < numlines; i++) begin
           for(j = 0; j < numways; j++) begin
+          if (CacheValid[j][i][0] & CacheDirty[j][i][0]) begin
             for(k = 0; k < numwords; k++) begin
-            if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
+              //cacheline = CacheData[j][i][0];
-            ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
+              // does not work with modelsim
+              // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
+              // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
+              //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
+              ShadowRAM[(CacheAdr[j][i][0] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][0][`XLEN*k +: `XLEN];
             end
           end	
           end
@@ -486,15 +494,15 @@ module DCacheFlushFSM
 endmodule
 
 module copyShadow
-  #(parameter tagstart, loglinebytelen)
+  #(parameter tagstart, loglinebytelen, linelen)
   (input logic clk,
    input logic 			     start,
    input logic [`PA_BITS-1:tagstart] tag,
    input logic 			     valid, dirty,
-   input logic [`XLEN-1:0] 	     data,
+   input logic [linelen-1:0] 	     data,
    input logic [32-1:0] 	     index,
    input logic [32-1:0] 	     cacheWord,
-   output logic [`XLEN-1:0] 	     CacheData,
+   output logic [linelen-1:0] 	     CacheData,
    output logic [`PA_BITS-1:0] 	     CacheAdr,
    output logic [`XLEN-1:0] 	     CacheTag,
    output logic 		     CacheValid,