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Renamed pagetablewalker to hptw

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This commit is contained in:
David Harris 2021-07-18 04:11:33 -04:00
parent c75d70126f
commit 8317be5aed
4 changed files with 9 additions and 9 deletions
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4
wally-pipelined/src/lsu/lsu.sv
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@ -151,7 +151,7 @@ module lsu
logic WalkerPageFaultM; logic WalkerPageFaultM;
pagetablewalker pagetablewalker( hptw hptw(
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.SATP_REGW(SATP_REGW), .SATP_REGW(SATP_REGW),
@ -184,7 +184,7 @@ module lsu
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM; assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
// arbiter between IEU and pagetablewalker // arbiter between IEU and hptw
lsuArb arbiter(.clk(clk), lsuArb arbiter(.clk(clk),
.reset(reset), .reset(reset),
// HPTW connection // HPTW connection

2
wally-pipelined/src/lsu/lsuArb.sv
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@ -83,7 +83,7 @@ module lsuArb
flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); // delay HPTWPAdr by a cycle flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); // delay HPTWPAdr by a cycle
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM; assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM; // *** DH: I don't understand this logic 7/18/21. Why should PCF ever go here?
assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE; assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE;
assign StallWtoDCache = SelPTW ? 1'b0 : StallW; assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
// always block interrupts when using the hardware page table walker. // always block interrupts when using the hardware page table walker.

11
wally-pipelined/src/mmu/pagetablewalker.sv → wally-pipelined/src/mmu/hptw.sv
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@ -1,8 +1,9 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// pagetablewalker.sv // hptw.sv
// //
// Written: tfleming@hmc.edu 2 March 2021 // Written: tfleming@hmc.edu 2 March 2021
// Modified: kmacsaigoren@hmc.edu 1 June 2021 // Modified: david_harris@hmc.edu 18 July 2021 cleanup and simplification
// kmacsaigoren@hmc.edu 1 June 2021
// implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment // implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
// adding support for terapage encoding, and for setting the TranslationPAdr using the new level, // adding support for terapage encoding, and for setting the TranslationPAdr using the new level,
// adding the internal SvMode signal // adding the internal SvMode signal
@ -29,7 +30,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module pagetablewalker module hptw
( (
input logic clk, reset, input logic clk, reset,
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
@ -83,7 +84,8 @@ module pagetablewalker
// State flops // State flops
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache assign PRegEn = HPTWRead & ~HPTWStall;
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
// Assign PTE descriptors common across all XLEN values // Assign PTE descriptors common across all XLEN values
// For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table // For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table
@ -96,7 +98,6 @@ module pagetablewalker
// Enable and select signals based on states // Enable and select signals based on states
assign StartWalk = (WalkerState == IDLE) & TLBMiss; assign StartWalk = (WalkerState == IDLE) & TLBMiss;
assign HPTWRead = (WalkerState == LEVEL3_READ) | (WalkerState == LEVEL2_READ) | (WalkerState == LEVEL1_READ) | (WalkerState == LEVEL0_READ); assign HPTWRead = (WalkerState == LEVEL3_READ) | (WalkerState == LEVEL2_READ) | (WalkerState == LEVEL1_READ) | (WalkerState == LEVEL0_READ);
assign PRegEn = HPTWRead & ~HPTWStall;
assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT); assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk; assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk; assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;

1
wally-pipelined/src/mmu/pmpadrdec.sv
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@ -41,7 +41,6 @@ module pmpadrdec (
output logic L, X, W, R output logic L, X, W, R
); );
localparam TOR = 2'b01; localparam TOR = 2'b01;
localparam NA4 = 2'b10; localparam NA4 = 2'b10;
localparam NAPOT = 2'b11; localparam NAPOT = 2'b11;