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Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts

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Domenico Ottolia 2021-04-29 20:42:14 -04:00
parent 893e03d55b
commit 830787e3e1
3 changed files with 14 additions and 4 deletions
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2
wally-pipelined/src/privileged/csrm.sv
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@ -97,7 +97,7 @@ module csrm #(parameter
); );
logic [`XLEN-1:0] MISA_REGW; logic [`XLEN-1:0] MISA_REGW;
logic [`XLEN-1:0] MSCRATCH_REGW,MCAUSE_REGW, MTVAL_REGW; logic [`XLEN-1:0] MSCRATCH_REGW, MCAUSE_REGW, MTVAL_REGW;
logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // 64-bit registers in RV64, or two 32-bit registers in RV32 logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // 64-bit registers in RV64, or two 32-bit registers in RV32
logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15]; // *** Might have to make 16 individual registers logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15]; // *** Might have to make 16 individual registers
//logic [`XLEN-1:0] PMPADDR0_REGW; //logic [`XLEN-1:0] PMPADDR0_REGW;

14
wally-pipelined/src/privileged/trap.sv
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@ -27,7 +27,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module trap ( module trap (
input logic reset, input logic clk, reset,
input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM, input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM, input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
@ -40,6 +40,7 @@ module trap (
input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
input logic [31:0] InstrM, input logic [31:0] InstrM,
input logic StallW,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
output logic InterruptM, output logic InterruptM,
output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
@ -74,11 +75,18 @@ module trap (
// Handle vectored traps (when mtvec/stvec/utvec csr value has bits [1:0] == 01) // Handle vectored traps (when mtvec/stvec/utvec csr value has bits [1:0] == 01)
// For vectored traps, set program counter to _tvec value + 4 times the cause code // For vectored traps, set program counter to _tvec value + 4 times the cause code
//
// POSSIBLE OPTIMIZATION:
// From 20190608 privielegd spec page 27 (3.1.7)
// > Allowing coarser alignments in Vectored mode enables vectoring to be
// > implemented without a hardware adder circuit.
// For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
// [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000}
generate generate
if(`VECTORED_INTERRUPTS_SUPPORTED) begin if(`VECTORED_INTERRUPTS_SUPPORTED) begin
always_comb always_comb
if (PrivilegedTrapVector[1:0] == 2'b01 && CauseM[`XLEN-1] == 1) if (PrivilegedTrapVector[1:0] == 2'b01 && CauseM[`XLEN-1] == 1)
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00}; PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {CauseM[`XLEN-5:0], 2'b00}, 2'b00};
else else
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
end end
@ -91,7 +99,7 @@ module trap (
if (mretM) PrivilegedNextPCM = MEPC_REGW; if (mretM) PrivilegedNextPCM = MEPC_REGW;
else if (sretM) PrivilegedNextPCM = SEPC_REGW; else if (sretM) PrivilegedNextPCM = SEPC_REGW;
else if (uretM) PrivilegedNextPCM = UEPC_REGW; else if (uretM) PrivilegedNextPCM = UEPC_REGW;
else PrivilegedNextPCM = PrivilegedTrapVector; else PrivilegedNextPCM = PrivilegedVectoredTrapVector;
// Cause priority defined in table 3.7 of 20190608 privileged spec // Cause priority defined in table 3.7 of 20190608 privileged spec
// Exceptions are of lower priority than all interrupts (3.1.9) // Exceptions are of lower priority than all interrupts (3.1.9)

2
wally-pipelined/testbench/testbench-imperas.sv
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@ -351,6 +351,7 @@ module testbench();
"rv64p/WALLY-SEPC", "4000", "rv64p/WALLY-SEPC", "4000",
"rv64p/WALLY-MTVAL", "6000", "rv64p/WALLY-MTVAL", "6000",
"rv64p/WALLY-STVAL", "4000", "rv64p/WALLY-STVAL", "4000",
"rv64p/WALLY-MTVEC", "2000",
"rv64p/WALLY-MARCHID", "4000", "rv64p/WALLY-MARCHID", "4000",
"rv64p/WALLY-MIMPID", "4000", "rv64p/WALLY-MIMPID", "4000",
"rv64p/WALLY-MHARTID", "4000", "rv64p/WALLY-MHARTID", "4000",
@ -371,6 +372,7 @@ module testbench();
"rv32p/WALLY-MHARTID", "4000", "rv32p/WALLY-MHARTID", "4000",
"rv32p/WALLY-MVENDORID", "4000" "rv32p/WALLY-MVENDORID", "4000"
//"rv32p/WALLY-MEDELEG", "4000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though. //"rv32p/WALLY-MEDELEG", "4000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though.
//"rv32p/WALLY-MTVEC", "2000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though.
}; };
string tests64periph[] = '{ string tests64periph[] = '{