diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv
index d9892f21d..fa5a6293e 100644
--- a/src/ebu/ahbinterface.sv
+++ b/src/ebu/ahbinterface.sv
@@ -29,7 +29,7 @@
 
 module ahbinterface #(
   parameter XLEN,
-  parameter LSU = 0                                   // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
+  parameter logic LSU = 1'b0                                   // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
 )( 
   input  logic                          HCLK, HRESETn,
   // bus interface
diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv
index a2d4e42b2..9ba159705 100644
--- a/src/ebu/busfsm.sv
+++ b/src/ebu/busfsm.sv
@@ -29,7 +29,7 @@
 
 // HCLK and clk must be the same clock!
 module busfsm #(
-  parameter READ_ONLY
+  parameter logic READ_ONLY
 )(
   input  logic       HCLK,
   input  logic       HRESETn,
@@ -72,7 +72,7 @@ module busfsm #(
 //                  (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here.  fails uart test, but i'm not sure the failure is valid.
                     (CurrState == DATA_PHASE); 
   
-  assign BusCommitted = CurrState != ADR_PHASE & ~(READ_ONLY & CurrState == MEM3);
+  assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY & CurrState == MEM3);
 
   assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE;
   assign HWRITE = BusRW[0];
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 107a4af8b..8e7d9a0d1 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -273,7 +273,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
       assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
       assign IFUHSIZE = 3'b010;
 
-      ahbinterface #(P.XLEN, 0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), 
+      ahbinterface #(P.XLEN, 1'b0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), 
         .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
         .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
         .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 06d64c154..cf0fab9e8 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -367,7 +367,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       assign LSUHADDR = PAdrM;
       assign LSUHSIZE = LSUFunct3M;
 
-      ahbinterface #(P.XLEN, 1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), 
+      ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), 
         .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
         .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
         .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));