From 825dbefcb24f0831c418b0fb5e124e123f5a1f00 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 12:26:03 -0500 Subject: [PATCH] Fixed bus width error. Have to check this FPGA to make sure this didn't break anything. --- src/rvvi/packetizer.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index 97c57415e..54dc9a27f 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -42,7 +42,7 @@ module packetizer import cvw::*; #(parameter cvw_t P, input logic RvviAxiWready ); - localparam TotalFrameLengthBits = 2*48+32+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12); + localparam TotalFrameLengthBits = 2*48+17+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12); localparam TotalFrameLengthBytes = TotalFrameLengthBits / 8; logic [9:0] WordCount; @@ -121,7 +121,7 @@ module packetizer import cvw::*; #(parameter cvw_t P, end assign Length = {4'b0, BytesInFrame}; - assign TotalFrame = {16'b0, rvviDelay, EthType, DstMac, SrcMac}; + assign TotalFrame = {17'b0, rvviDelay, EthType, DstMac, SrcMac}; // *** fix me later assign DstMac = 48'h8F54_0000_1654; // made something up