From 822e60bd3dd381b4da0d515b75ddcb792275b5ac Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 5 Jun 2023 15:42:05 -0500 Subject: [PATCH] Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. --- src/privileged/csrc.sv | 2 +- testbench/testbench.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index e7e50a7d3..e1104f699 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -98,7 +98,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions - assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong + assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 6184cefb0..bffd80b96 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -554,7 +554,7 @@ module testbench; always @(*) begin if(reset) begin for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin - force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; end for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;