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@ -215,6 +215,7 @@ module lsu (
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assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
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assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
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assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
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assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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// *** add ce to bram1... to remove this extra mux control.
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dtim dtim(.clk, .reset, .MemRWM,
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dtim dtim(.clk, .reset, .MemRWM,
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.Adr(DTIMAdr),
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.Adr(DTIMAdr),
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