diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do
index 9318c494a..64e20c1f2 100644
--- a/wally-pipelined/regression/wally-coremark_bare.do
+++ b/wally-pipelined/regression/wally-coremark_bare.do
@@ -54,7 +54,7 @@ add wave -divider
 
 add wave -divider Fetch
 add wave -hex /testbench/dut/hart/ifu/PCF
-add wave -hex /testbench/dut/hart/ifu/InstrF
+add wave -hex /testbench/dut/hart/ifu/ic/InstrF
 add wave /testbench/InstrFName
 add wave -divider Decode
 add wave -hex /testbench/dut/hart/ifu/PCD
@@ -93,7 +93,7 @@ add wave -divider RAM
 add wave -hex -r /testbench/dut/uncore/dtim/RAM
 add wave -divider Misc
 add wave -divider
-#add wave -hex -r /testbench/*
+add wave -hex -r /testbench/*
 
 -- Set Wave Output Items 
 TreeUpdate [SetDefaultTree]
diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index 3f2af76b6..860820bfd 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -48,7 +48,7 @@ module testbench();
   
   // pick tests based on modes supported
   initial 
-  tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"};
+  tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"};
   string signame, memfilename;
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
@@ -65,7 +65,7 @@ module testbench();
 
   // Track names of instructions
   instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
-                dut.hart.ifu.InstrF,
+                dut.hart.ifu.ic.InstrF,
                 dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
                 dut.hart.ifu.InstrM, InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);