From 90040a6a217ae38c61b95d17107898833e2b3b42 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 9 Apr 2024 16:13:31 -0700 Subject: [PATCH 1/4] Added extra path to run-imperas-linux.sh to match new questa directory with .do files --- sim/run-imperas-linux.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh index 65e4826fb..7192adb81 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/run-imperas-linux.sh @@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100" #export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" #export OTHERFLAGS="" -vsim -c -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0" +vsim -c -do "do questa/wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0" From 342c99d6ead625923cec17bff1e1b25e70966900 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 12 Apr 2024 21:30:33 -0700 Subject: [PATCH 2/4] Rearranged uart_logger block to only generate if UART is supported --- testbench/testbench.sv | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 035e625b7..9a2772fb5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -580,12 +580,14 @@ module testbench; end // Append UART output to file for tests - always @(posedge clk) begin - if (P.UART_SUPPORTED & TEST == "buildroot") begin - if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin - memFile = $fopen(uartoutfilename, "ab"); - $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din); - $fclose(memFile); + if (P.UART_SUPPORTED) begin: uart_logger + always @(posedge clk) begin + if (TEST == "buildroot") begin + if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin + memFile = $fopen(uartoutfilename, "ab"); + $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din); + $fclose(memFile); + end end end end From 4b80457f3e37cca91f4680f55a2e6c0f996952e5 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 12 Apr 2024 21:58:20 -0700 Subject: [PATCH 3/4] Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory --- sim/{ => questa}/run-imperas-linux.sh | 0 src/uncore/uart_apb.sv | 2 +- src/uncore/uncore.sv | 2 +- src/wally/wallypipelinedsoc.sv | 2 +- testbench/testbench.sv | 24 ++++++++++++------------ 5 files changed, 15 insertions(+), 15 deletions(-) rename sim/{ => questa}/run-imperas-linux.sh (100%) diff --git a/sim/run-imperas-linux.sh b/sim/questa/run-imperas-linux.sh similarity index 100% rename from sim/run-imperas-linux.sh rename to sim/questa/run-imperas-linux.sh diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv index eeecb7ea5..c3f8bb31c 100644 --- a/src/uncore/uart_apb.sv +++ b/src/uncore/uart_apb.sv @@ -60,7 +60,7 @@ module uart_apb import cvw::*; #(parameter cvw_t P) ( else assign PRDATA = {Dout, Dout, Dout, Dout}; logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK - uartPC16550D #(P.UART_PRESCALE) u( + uartPC16550D #(P.UART_PRESCALE) uartPC( // Processor Interface .PCLK, .PRESETn, .A(entry), .Din, diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 22e0a35fc..edebe05c7 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -139,7 +139,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( end else begin : gpio assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0; end - if (P.UART_SUPPORTED == 1) begin : uart + if (P.UART_SUPPORTED == 1) begin : u uart_apb #(P) uart( .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index d82a5c0d4..980b69e03 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -79,7 +79,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( ); // instantiate uncore if a bus interface exists - if (P.BUS_SUPPORTED) begin : uncore + if (P.BUS_SUPPORTED) begin : uc uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 9a2772fb5..07bc6805e 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -429,10 +429,10 @@ module testbench; string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; - //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); + //$readmemh(romfilename, dut.uc.uncore.bootrom.bootrom.memory.ROM); //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation - //dut.uncore.uncore.sdc.SDC.LimitTimers = 1; + //dut.uc.uncore.sdc.SDC.LimitTimers = 1; end end end else if (P.IROM_SUPPORTED) begin @@ -446,13 +446,13 @@ module testbench; if (LoadMem) begin if (TEST == "buildroot") begin memFile = $fopen(bootmemfilename, "rb"); - readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile); + readResult = $fread(dut.uc.uncore.bootrom.bootrom.memory.ROM, memFile); $fclose(memFile); memFile = $fopen(memfilename, "rb"); - readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile); + readResult = $fread(dut.uc.uncore.ram.ram.memory.RAM, memFile); $fclose(memFile); end else - $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + $readmemh(memfilename, dut.uc.uncore.ram.ram.memory.RAM); if (TEST == "embench") $display("Read memfile %s", memfilename); end if (CopyRAM) begin @@ -461,7 +461,7 @@ module testbench; EndIndex = (end_signature_addr >> LogXLEN) + 8; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin - testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; + testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uc.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; end end end @@ -489,7 +489,7 @@ module testbench; always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0; + dut.uc.uncore.ram.ram.memory.RAM[adrindex] = 0; //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -583,9 +583,9 @@ module testbench; if (P.UART_SUPPORTED) begin: uart_logger always @(posedge clk) begin if (TEST == "buildroot") begin - if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin + if (~dut.uc.uncore.u.uart.MEMWb & dut.uc.uncore.u.uart.uartPC.A == 3'b000 & ~dut.uc.uncore.u.uart.uartPC.DLAB) begin memFile = $fopen(uartoutfilename, "ab"); - $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din); + $fwrite(memFile, "%c", dut.uc.uncore.u.uart.uartPC.Din); $fclose(memFile); end end @@ -859,9 +859,9 @@ end // ************************************** // ***** BUG BUG BUG make sure RT undoes this. //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; - //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uc.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uc.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uc.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin From 39ae26a897d95ef467c51822dcbb9f9dbee304ea Mon Sep 17 00:00:00 2001 From: slmnemo Date: Mon, 15 Apr 2024 15:58:09 -0700 Subject: [PATCH 4/4] Added documentation for known Verilator hierarchy bug --- src/uncore/uncore.sv | 2 +- src/wally/wallypipelinedsoc.sv | 2 +- testbench/testbench.sv | 24 ++++++++++++------------ 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index edebe05c7..97099d0e2 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -139,7 +139,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( end else begin : gpio assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0; end - if (P.UART_SUPPORTED == 1) begin : u + if (P.UART_SUPPORTED == 1) begin : uartgen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769 uart_apb #(P) uart( .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 980b69e03..8e223f858 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -79,7 +79,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( ); // instantiate uncore if a bus interface exists - if (P.BUS_SUPPORTED) begin : uc + if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769 uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 07bc6805e..ee5b1e11f 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -429,10 +429,10 @@ module testbench; string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; - //$readmemh(romfilename, dut.uc.uncore.bootrom.bootrom.memory.ROM); + //$readmemh(romfilename, dut.uncoregen.uncore.bootrom.bootrom.memory.ROM); //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation - //dut.uc.uncore.sdc.SDC.LimitTimers = 1; + //dut.uncoregen.uncore.sdc.SDC.LimitTimers = 1; end end end else if (P.IROM_SUPPORTED) begin @@ -446,13 +446,13 @@ module testbench; if (LoadMem) begin if (TEST == "buildroot") begin memFile = $fopen(bootmemfilename, "rb"); - readResult = $fread(dut.uc.uncore.bootrom.bootrom.memory.ROM, memFile); + readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile); $fclose(memFile); memFile = $fopen(memfilename, "rb"); - readResult = $fread(dut.uc.uncore.ram.ram.memory.RAM, memFile); + readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.RAM, memFile); $fclose(memFile); end else - $readmemh(memfilename, dut.uc.uncore.ram.ram.memory.RAM); + $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.RAM); if (TEST == "embench") $display("Read memfile %s", memfilename); end if (CopyRAM) begin @@ -461,7 +461,7 @@ module testbench; EndIndex = (end_signature_addr >> LogXLEN) + 8; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin - testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uc.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; + testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; end end end @@ -489,7 +489,7 @@ module testbench; always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uc.uncore.ram.ram.memory.RAM[adrindex] = 0; + dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = 0; //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -583,9 +583,9 @@ module testbench; if (P.UART_SUPPORTED) begin: uart_logger always @(posedge clk) begin if (TEST == "buildroot") begin - if (~dut.uc.uncore.u.uart.MEMWb & dut.uc.uncore.u.uart.uartPC.A == 3'b000 & ~dut.uc.uncore.u.uart.uartPC.DLAB) begin + if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin memFile = $fopen(uartoutfilename, "ab"); - $fwrite(memFile, "%c", dut.uc.uncore.u.uart.uartPC.Din); + $fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); $fclose(memFile); end end @@ -859,9 +859,9 @@ end // ************************************** // ***** BUG BUG BUG make sure RT undoes this. //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; - //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uc.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uc.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uc.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin