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				@ -140,6 +140,10 @@ string tests64iNOc[] = {
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                     "rv64i/WALLY-LOAD", "11bf0",
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					                     "rv64i/WALLY-LOAD", "11bf0",
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                     "rv64i/WALLY-JAL", "4000",
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					                     "rv64i/WALLY-JAL", "4000",
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                     "rv64i/WALLY-STORE", "3000"
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					                     "rv64i/WALLY-STORE", "3000"
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							     "rv64i/WALLY-ADDIW", "3000",
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							     "rv64i/WALLY-SLLIW", "3000",
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							     "rv64i/WALLY-SRLIW", "3000",
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							     "rv64i/WALLY-SRAIW", "3000"
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  };
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					  };
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string tests32ic[] = '{
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					string tests32ic[] = '{
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//                     "rv32ic/WALLY-C-ADHOC-01", "2000",
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					//                     "rv32ic/WALLY-C-ADHOC-01", "2000",
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										182
									
								
								wally-pipelined/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
									
									
									
									
									
										Executable file
									
								
							
							
						
						
									
										182
									
								
								wally-pipelined/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
									
									
									
									
									
										Executable file
									
								
							@ -0,0 +1,182 @@
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					#!/usr/bin/python3
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					##################################
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					# testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
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					#
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					# ehedenberg@hmc.edu 4 February 2021
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					# heavily influenced by Prof Harris Code
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					#
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					# Generate directed and random test vectors for RISC-V Design Validation.
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					##################################
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					##################################
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					# libraries
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					##################################
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					from datetime import datetime
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					from random import randint 
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					from random import seed
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					from random import getrandbits
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					import sys
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					##################################
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					# functions
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					##################################
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					def logical_rshift(signed_integer, places):
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					  unsigned_integer=signed_integer%(1<<32)
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					  return unsigned_integer >> places
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					def toSigned12bit(n):
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					  n=n & 0xfff
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					  if (n&(1<<11)):
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					    n=n|0xfffffffffffff000
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					  return n
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					def toSigned32bit(n):
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					  n=n & 0xffffffff
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					  if (n&(1<<31)):
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					    n=n|0xffffffff00000000
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					  return n
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					def computeExpected(a, b, test):
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					  if (test == "ADDIW"):
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					    b=toSigned12bit(b)
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					    return a + b
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					  elif (test == "SLLIW"):
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					    return (a << b)
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					  elif (test == "SRLIW"):
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					    return logical_rshift(a, b)
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					  elif(test == "SRAIW"):
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					    a= toSigned32bit(a)
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					    return a >> b
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					  else:
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					    die("bad test name ", test)
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					  #  exit(1)
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					def randRegs():
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					  reg1 = randint(1,31)
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					  reg2 = randint(1,31)
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					  reg3 = randint(1,31) 
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					  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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					    return randRegs()
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					  else:
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					      return reg1, reg2, reg3
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					def writeVector(a, b, storecmd):
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					  global testnum
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					  expected = computeExpected(a, b, test)
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					  expected = expected % 2**64 # drop carry if necessary
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					  if (expected < 0): # take twos complement
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					    expected = 2**64 + expected
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					    #expected=expected+2^32<<32
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					  if (expected >= (2**32)):
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					    expected=expected%(2**32)
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					  expected=toSigned32bit(expected)
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					  reg1, reg2, reg3 = randRegs()
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					  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
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					  lines = lines + "), imm:"+formatstr.format(b) 
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					  lines = lines + ", result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
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					  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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					  #lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
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					  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", SEXT_IMM(" + formatstr.format(b) + ")\n"
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					  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
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					  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, x" + str(reg3) +", "+formatstr.format(expected)+")\n"
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					  #lines = lines + str(b)+"\n"
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					  f.write(lines)
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					  if (xlen == 32):
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					    line = formatrefstr.format(expected)+"\n"
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					  else:
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					    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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					  r.write(line)
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					  testnum = testnum+1
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					##################################
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					# main body
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					##################################
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					# change these to suite your tests
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					tests = ["ADDIW", "SLLIW", "SRLIW", "SRAIW"]
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					author = "Eizabeth Hedenberg"
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					xlens = [64]
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					shiftlen=5
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					addlen=12
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					numrand = 100
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					# setup
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					seed(0) # make tests reproducible
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					# generate files for each test
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					for xlen in xlens:
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					  formatstrlen = str(int(xlen/4))
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					  #formatstrlen6=str(int())
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					  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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					  #formatstr6 = "0x{:0" + "2" + "x}" # format as xlen-bit hexadecimal number
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					  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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					  if (xlen == 32):
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					    storecmd = "sw"
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					    wordsize = 4
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					  else:
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					    storecmd = "sd"
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					    wordsize = 8
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					  for test in tests:
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					    cornersa = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
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					            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
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					            #test both confined to top 32 and not
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					    cornersshift=[0, 1, 2, 2**(shiftlen)-1, 2**(shiftlen)-2, 0b00101, 0b01110]
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					    #6 bits: 0, 1, 2, largest, largest -1, largest -2,  21, 46
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					    cornersadd=[0, 1, 2, 2**(addlen-1), 2**(addlen-1)-1, 2**(addlen-1)-2, 2**(addlen-1)+1, 2**(addlen)-2, 2**(addlen)-1, 0b001010010101, 0b101011101111]
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					    #12 bit, 0, 1, 2 argest positive, largest -1, largest -2, largest negative number, -2, -1, random
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					    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
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					    basename = "WALLY-" + test 
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					    fname = imperaspath + "src/" + basename + ".S"
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					    refname = imperaspath + "references/" + basename + ".reference_output"
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					    testnum = 0
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					    # print custom header part
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					    f = open(fname, "w")
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					    r = open(refname, "w")
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					    line = "///////////////////////////////////////////\n"
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					    f.write(line)
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					    lines="// "+fname+ "\n// " + author + "\n"
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					    f.write(lines)
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					    line ="// Created " + str(datetime.now()) 
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					    f.write(line)
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					    # insert generic header
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					    h = open("testgen_header.S", "r")
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					    for line in h:  
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					      f.write(line)
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					    # print directed and random test vectors
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					    if test=="ADDIW":
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					      for a in cornersa:
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					        for b in cornersadd:
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					          writeVector(a, b, storecmd)
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					      for i in range(0,numrand):
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					        a = getrandbits(xlen)
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					        b = getrandbits(12)
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					        writeVector(a, b, storecmd)
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					    else:
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					      for a in cornersa:
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					        for b in cornersshift:
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					          writeVector(a, b, storecmd)
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					      for i in range(0,numrand):
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					        a = getrandbits(xlen)
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					        b = getrandbits(5)
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					        writeVector(a, b, storecmd)
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					    # print footer
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					    h = open("testgen_footer.S", "r")
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					    for line in h:  
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					      f.write(line)
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					    # Finish
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					    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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					    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
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					    f.write(lines)
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					    f.close()
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					    r.close()
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