Lint cleanup: ahblite, ifu, hart

wally-pipelined/src/ebu/ahblite.sv

@@ -36,11 +36,9 @@ endpackage
 
 module ahblite (
   input logic 		     clk, reset,
-  input logic 		     StallW,
   // Load control
   input logic 		     UnsignedLoadM,
   input logic [1:0] 	     AtomicMaskedM,
-  input logic [6:0] 	     Funct7M,
   // Signals from Instruction Cache
   input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram
   input logic 		     InstrReadF,
@@ -75,14 +73,11 @@ module ahblite (
   logic GrantData;
   logic [31:0] AccessAddress;
   logic [2:0] ISize;
-  logic [`AHBW-1:0] HRDATAMasked, ReadDataM, HRDATANext, CapturedHRDATAMasked, WriteData;
-  logic IReady, DReady;
-  logic CaptureDataM,CapturedDataAvailable;
 
   assign HCLK = clk;
   assign HRESETn = ~reset;
 
-  // *** initially support AHBW = XLEN
+  // initially support AHBW = XLEN
 
   // track bus state
   // Data accesses have priority over instructions.  However, if a data access comes

wally-pipelined/src/ifu/ifu.sv

@@ -76,15 +76,13 @@ module ifu (
   input logic 		      ITLBWriteF, ITLBFlushF,
   input logic 		      WalkerInstrPageFaultF,
 
-  output logic 		      ITLBMissF, ITLBHitF,
+  output logic 		      ITLBMissF,
 
   // pmp/pma (inside mmu) signals.  *** temporarily from AHB bus but eventually replace with internal versions pre H
   input  var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
   input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], 
 
-  output logic InstrAccessFaultF,
+  output logic InstrAccessFaultF
-
-  output logic 		      ISquashBusAccessF
 );
 
   logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -94,8 +94,7 @@ module wallypipelinedhart
   logic 		    SquashSCM, SquashSCW;
   // floating point unit signals
   logic [2:0] 		    FRM_REGW;
-  logic [1:0] 		    FMemRWM, FMemRWE;
+   logic [4:0]        RdE, RdM, RdW;
-  logic [4:0]        RdE, RdM, RdW;
   logic 		    FStallD;
   logic 		    FWriteIntE, FWriteIntM, FWriteIntW;
   logic [`XLEN-1:0] 	    FWriteDataE;
@@ -108,10 +107,10 @@ module wallypipelinedhart
   logic [`XLEN-1:0] 	    FPUResultW;
 
   // memory management unit signals
-  logic 		    ITLBWriteF, DTLBWriteM;
+  logic 		    ITLBWriteF;
   logic 		    ITLBFlushF, DTLBFlushM;
-  logic 		    ITLBMissF, ITLBHitF;
+  logic 		    ITLBMissF;
-  logic 		    DTLBMissM, DTLBHitM;
+  logic 		    DTLBHitM;
   logic [`XLEN-1:0] 	    SATP_REGW;
   logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV;
   logic  [1:0]       STATUS_MPP;
@@ -120,7 +119,6 @@ module wallypipelinedhart
   logic [1:0] 		    PageType;
 
   // PMA checker signals
-  logic 		    DSquashBusAccessM, ISquashBusAccessF;
   var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
   var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
 
@@ -233,9 +231,6 @@ module wallypipelinedhart
 	  .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
 	  .WalkerLoadPageFaultM(WalkerLoadPageFaultM),
 	  .WalkerStorePageFaultM(WalkerStorePageFaultM),
-
-	  .DTLBHitM(DTLBHitM), // not connected remove
-
 	  .LSUStall(LSUStall));                     // change to LSUStall
 
 
@@ -256,9 +251,6 @@ module wallypipelinedhart
 	      // remove these
 	      .MemSizeM(DCtoAHBSizeM[1:0]),  // *** depends on XLEN  should be removed
 	      .UnsignedLoadM(1'b0),
-	      .Funct7M(7'b0),
-//	      .HRDATAW(),
-	      .StallW(1'b0),
 	      .AtomicMaskedM(2'b00),
 	       .*);
 
@@ -272,9 +264,5 @@ module wallypipelinedhart
   
 
   fpu fpu(.*); // floating point unit
-  // add FPU here, with SetFflagsM, FRM_REGW
-  // presently stub out SetFlagsM and FRegWriteM
-  //assign SetFflagsM = 0;
-  //assign FRegWriteM = 0;
   
 endmodule