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More cleanup.

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This commit is contained in:
Ross Thompson 2022-08-31 11:12:38 -05:00
parent 4b167ad21e
commit 8156109add
4 changed files with 48 additions and 53 deletions
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94
pipelined/src/cache/AHBBuscachefsm.sv vendored
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@ -32,8 +32,8 @@
// HCLK and clk must be the same clock! // HCLK and clk must be the same clock!
module AHBBuscachefsm #(parameter integer WordCountThreshold, module AHBBuscachefsm #(parameter integer WordCountThreshold,
parameter integer LOGWPL, parameter logic CACHE_ENABLED ) parameter integer LOGWPL, parameter logic CACHE_ENABLED )
(input logic HCLK, (input logic HCLK,
input logic HRESETn, input logic HRESETn,
// IEU interface // IEU interface
@ -48,7 +48,6 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
output logic CacheBusAck, output logic CacheBusAck,
// lsu interface // lsu interface
input logic Cacheable,
output logic SelUncachedAdr, output logic SelUncachedAdr,
output logic [LOGWPL-1:0] WordCount, WordCountDelayed, output logic [LOGWPL-1:0] WordCount, WordCountDelayed,
output logic SelBusWord, output logic SelBusWord,
@ -71,14 +70,38 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
(* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
logic WordCntEn; logic [LOGWPL-1:0] NextWordCount;
logic [LOGWPL-1:0] NextWordCount; logic FinalWordCount;
logic WordCountFlag; logic [2:0] LocalBurstType;
logic [2:0] LocalBurstType; logic WordCntEn;
logic WordCntReset; logic WordCntReset;
logic CacheAccess; logic CacheAccess;
// Used to send address for address stage of AHB. always_ff @(posedge HCLK)
if (~HRESETn) BusCurrState <= #1 STATE_READY;
else BusCurrState <= #1 BusNextState;
always_comb begin
case(BusCurrState)
STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE;
else if (HREADY & CacheRW[0]) BusNextState = STATE_CACHE_EVICT;
else if (HREADY & CacheRW[1]) BusNextState = STATE_CACHE_FETCH;
else BusNextState = STATE_READY;
STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY;
else BusNextState = STATE_CAPTURE;
STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
else BusNextState = STATE_READY;
STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
else BusNextState = STATE_READY;
STATE_CACHE_FETCH: if(HREADY & FinalWordCount) BusNextState = STATE_READY;
else BusNextState = STATE_CACHE_FETCH;
STATE_CACHE_EVICT: if(HREADY & FinalWordCount) BusNextState = STATE_READY;
else BusNextState = STATE_CACHE_EVICT;
default: BusNextState = STATE_READY;
endcase
end
// IEU, LSU, and IFU controls
flopenr #(LOGWPL) flopenr #(LOGWPL)
WordCountReg(.clk(HCLK), WordCountReg(.clk(HCLK),
.reset(~HRESETn | WordCntReset), .reset(~HRESETn | WordCntReset),
@ -95,54 +118,31 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
.q(WordCountDelayed)); .q(WordCountDelayed));
assign NextWordCount = WordCount + 1'b1; assign NextWordCount = WordCount + 1'b1;
assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access. assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0];
assign WordCntEn = ((BusNextState == STATE_CACHE_EVICT | BusNextState == STATE_CACHE_FETCH) & HREADY) | assign WordCntEn = ((BusNextState == STATE_CACHE_EVICT | BusNextState == STATE_CACHE_FETCH) & HREADY) |
(BusNextState == STATE_READY & |CacheRW & HREADY); (BusNextState == STATE_READY & |CacheRW & HREADY);
assign WordCntReset = BusNextState == STATE_READY; assign WordCntReset = BusNextState == STATE_READY;
always_ff @(posedge HCLK) assign CaptureEn = (BusCurrState == STATE_CAPTURE & RW[1]) | (BusCurrState == STATE_CACHE_FETCH & HREADY);
if (~HRESETn) BusCurrState <= #1 STATE_READY; assign CacheAccess = BusCurrState == STATE_CACHE_FETCH | BusCurrState == STATE_CACHE_EVICT;
else BusCurrState <= #1 BusNextState;
always_comb begin
case(BusCurrState)
STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE;
else if (HREADY & CacheRW[0]) BusNextState = STATE_CACHE_EVICT;
else if (HREADY & CacheRW[1]) BusNextState = STATE_CACHE_FETCH;
else BusNextState = STATE_READY;
STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY;
else BusNextState = STATE_CAPTURE;
STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
else BusNextState = STATE_READY;
STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
else BusNextState = STATE_READY;
STATE_CACHE_FETCH: if(HREADY & WordCountFlag) BusNextState = STATE_READY;
else BusNextState = STATE_CACHE_FETCH;
STATE_CACHE_EVICT: if(HREADY & WordCountFlag) BusNextState = STATE_READY;
else BusNextState = STATE_CACHE_EVICT;
default: BusNextState = STATE_READY;
endcase
end
assign CacheAccess = (BusCurrState == STATE_CACHE_FETCH) | (BusCurrState == STATE_CACHE_EVICT);
assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) | assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) |
(BusCurrState == STATE_CAPTURE) | (BusCurrState == STATE_CAPTURE) |
(BusCurrState == STATE_CACHE_FETCH) | (BusCurrState == STATE_CACHE_FETCH) |
(BusCurrState == STATE_CACHE_EVICT); (BusCurrState == STATE_CACHE_EVICT);
assign BusCommitted = BusCurrState != STATE_READY;
assign SelUncachedAdr = (BusCurrState == STATE_READY & |RW) |
(BusCurrState == STATE_CAPTURE) |
(BusCurrState == STATE_DELAY);
assign BusCommitted = BusCurrState != STATE_READY; // *** might not be correct // AHB bus interface
assign HTRANS = (BusCurrState == STATE_READY & HREADY & (|RW | |CacheRW)) | assign HTRANS = (BusCurrState == STATE_READY & HREADY & (|RW | |CacheRW)) |
(BusCurrState == STATE_CAPTURE & ~HREADY) | (BusCurrState == STATE_CAPTURE & ~HREADY) |
(CacheAccess & ~HREADY & ~|WordCount) ? AHB_NONSEQ : (CacheAccess & ~HREADY & ~|WordCount) ? AHB_NONSEQ :
(CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE; (CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE;
assign HWRITE = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | // *** might not be necessary, maybe just RW[0] | CacheRW[0]? assign HWRITE = RW[0] | CacheRW[0];
(BusCurrState == STATE_CACHE_EVICT); assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0;
assign CaptureEn = (BusCurrState == STATE_CAPTURE & RW[1]) | (BusCurrState == STATE_CACHE_FETCH & HREADY);
assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0; // Don't want to use burst when doing an Uncached Access.
always_comb begin always_comb begin
case(WordCountThreshold) case(WordCountThreshold)
@ -154,12 +154,8 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
endcase endcase
end end
assign SelUncachedAdr = (BusCurrState == STATE_READY & |RW) | // communication to cache
(BusCurrState == STATE_CAPTURE) | assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount);
(BusCurrState == STATE_DELAY);
assign CacheBusAck = (CacheAccess & HREADY & WordCountFlag);
assign SelBusWord = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | assign SelBusWord = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) |
(BusCurrState == STATE_CAPTURE & RW[0]) | (BusCurrState == STATE_CAPTURE & RW[0]) |
(BusCurrState == STATE_CACHE_EVICT); (BusCurrState == STATE_CACHE_EVICT);

3
pipelined/src/cache/AHBCachedp.sv vendored
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@ -59,7 +59,6 @@ module AHBCachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
input logic [`PA_BITS-1:0] PAdr, input logic [`PA_BITS-1:0] PAdr,
input logic [1:0] RW, input logic [1:0] RW,
input logic CPUBusy, input logic CPUBusy,
input logic Cacheable,
input logic [2:0] Funct3, input logic [2:0] Funct3,
output logic SelBusWord, output logic SelBusWord,
output logic BusStall, output logic BusStall,
@ -85,6 +84,6 @@ module AHBCachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
.HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, .HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
.CacheRW, .CacheBusAck, .Cacheable, .SelUncachedAdr, .WordCount, .WordCountDelayed, .CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST); .HREADY, .HTRANS, .HWRITE, .HBURST);
endmodule endmodule

2
pipelined/src/ifu/ifu.sv
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@ -235,7 +235,7 @@ module ifu (
.WordCount(), .SelUncachedAdr, .SelBusWord(), .WordCount(), .SelUncachedAdr, .SelBusWord(),
.CacheBusAck(ICacheBusAck), .CacheBusAck(ICacheBusAck),
.FetchBuffer, .PAdr(PCPF), .FetchBuffer, .PAdr(PCPF),
.RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF}), .CPUBusy, .Cacheable(CacheableF), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF}), .CPUBusy,
.BusStall, .BusCommitted()); .BusStall, .BusCommitted());
mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]), mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),

2
pipelined/src/lsu/lsu.sv
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@ -262,7 +262,7 @@ module lsu (
.WordCount, .SelBusWord, .WordCount, .SelBusWord,
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheRW({DCacheFetchLine, DCacheWriteLine} & ~{IgnoreRequest, IgnoreRequest}), .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheRW({DCacheFetchLine, DCacheWriteLine} & ~{IgnoreRequest, IgnoreRequest}),
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM),
.SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM}), .CPUBusy, .Cacheable(CacheableM), .SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM}), .CPUBusy,
.BusStall, .BusCommitted(BusCommittedM)); .BusStall, .BusCommitted(BusCommittedM));
mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }),