More cleanup.

pipelined/src/cache/AHBBuscachefsm.sv

@@ -48,7 +48,6 @@ module AHBBuscachefsm #(parameter integer   WordCountThreshold,
    output logic              CacheBusAck,
    
    // lsu interface
-   input logic               Cacheable,
    output logic              SelUncachedAdr,
    output logic [LOGWPL-1:0] WordCount, WordCountDelayed,
    output logic              SelBusWord,
@@ -71,35 +70,13 @@ module AHBBuscachefsm #(parameter integer   WordCountThreshold,
 
   (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
 
-  logic        WordCntEn;
   logic [LOGWPL-1:0] NextWordCount;
-  logic                WordCountFlag;
+  logic              FinalWordCount;
   logic [2:0]        LocalBurstType;
+  logic              WordCntEn;
   logic              WordCntReset;
   logic              CacheAccess;
   
-  // Used to send address for address stage of AHB.
-  flopenr #(LOGWPL) 
-  WordCountReg(.clk(HCLK),
-		.reset(~HRESETn | WordCntReset),
-		.en(WordCntEn),
-		.d(NextWordCount),
-		.q(WordCount));  
-  
-  // Used to store data from data phase of AHB.
-  flopenr #(LOGWPL) 
-  WordCountDelayedReg(.clk(HCLK),
-		.reset(~HRESETn | WordCntReset),
-		.en(WordCntEn),
-		.d(WordCount),
-		.q(WordCountDelayed));
-  assign NextWordCount = WordCount + 1'b1;
-
-  assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access.
-  assign WordCntEn = ((BusNextState == STATE_CACHE_EVICT | BusNextState == STATE_CACHE_FETCH) & HREADY) |
-                     (BusNextState == STATE_READY & |CacheRW & HREADY);
-  assign WordCntReset = BusNextState == STATE_READY;
-
   always_ff @(posedge HCLK)
     if (~HRESETn)    BusCurrState <= #1 STATE_READY;
     else BusCurrState <= #1 BusNextState;  
@@ -116,33 +93,56 @@ module AHBBuscachefsm #(parameter integer   WordCountThreshold,
 		           else                          BusNextState = STATE_READY;
       STATE_CPU_BUSY: if(CPUBusy)                BusNextState = STATE_CPU_BUSY;
                    else                          BusNextState = STATE_READY;
-      STATE_CACHE_FETCH: if(HREADY & WordCountFlag) BusNextState = STATE_READY;
+      STATE_CACHE_FETCH: if(HREADY & FinalWordCount) BusNextState = STATE_READY;
                          else                       BusNextState = STATE_CACHE_FETCH;
-      STATE_CACHE_EVICT: if(HREADY & WordCountFlag) BusNextState = STATE_READY;
+      STATE_CACHE_EVICT: if(HREADY & FinalWordCount) BusNextState = STATE_READY;
                          else                       BusNextState = STATE_CACHE_EVICT;
 	  default:                                      BusNextState = STATE_READY;
 	endcase
   end
 
-  assign CacheAccess = (BusCurrState == STATE_CACHE_FETCH) | (BusCurrState == STATE_CACHE_EVICT);
+  // IEU, LSU, and IFU controls
+  flopenr #(LOGWPL) 
+  WordCountReg(.clk(HCLK),
+		.reset(~HRESETn | WordCntReset),
+		.en(WordCntEn),
+		.d(NextWordCount),
+		.q(WordCount));  
   
+  // Used to store data from data phase of AHB.
+  flopenr #(LOGWPL) 
+  WordCountDelayedReg(.clk(HCLK),
+		.reset(~HRESETn | WordCntReset),
+		.en(WordCntEn),
+		.d(WordCount),
+		.q(WordCountDelayed));
+  assign NextWordCount = WordCount + 1'b1;
+
+  assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0];
+  assign WordCntEn = ((BusNextState == STATE_CACHE_EVICT | BusNextState == STATE_CACHE_FETCH) & HREADY) |
+                     (BusNextState == STATE_READY & |CacheRW & HREADY);
+  assign WordCntReset = BusNextState == STATE_READY;
+
+  assign CaptureEn = (BusCurrState == STATE_CAPTURE & RW[1]) | (BusCurrState == STATE_CACHE_FETCH & HREADY);
+  assign CacheAccess = BusCurrState == STATE_CACHE_FETCH | BusCurrState == STATE_CACHE_EVICT;
 
   assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) |
 					(BusCurrState == STATE_CAPTURE) | 
                     (BusCurrState == STATE_CACHE_FETCH) |
                     (BusCurrState == STATE_CACHE_EVICT);
+  assign BusCommitted = BusCurrState != STATE_READY;
+  assign SelUncachedAdr = (BusCurrState == STATE_READY & |RW) |
+                          (BusCurrState == STATE_CAPTURE) |
+                          (BusCurrState == STATE_DELAY);
 
-  assign BusCommitted = BusCurrState != STATE_READY; // *** might not be correct
+  // AHB bus interface
-
   assign HTRANS = (BusCurrState == STATE_READY & HREADY & (|RW | |CacheRW)) |
                   (BusCurrState == STATE_CAPTURE & ~HREADY) |
                   (CacheAccess & ~HREADY & ~|WordCount) ? AHB_NONSEQ :
                   (CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE;
 
-  assign HWRITE = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) |  // *** might not be necessary, maybe just RW[0] | CacheRW[0]?
+  assign HWRITE = RW[0] | CacheRW[0];
-                  (BusCurrState == STATE_CACHE_EVICT);
+  assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0;
-  assign CaptureEn = (BusCurrState == STATE_CAPTURE & RW[1]) | (BusCurrState == STATE_CACHE_FETCH & HREADY);
-  assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0; // Don't want to use burst when doing an Uncached Access.
   
   always_comb begin
     case(WordCountThreshold)
@@ -154,12 +154,8 @@ module AHBBuscachefsm #(parameter integer   WordCountThreshold,
     endcase
   end
 
-  assign SelUncachedAdr = (BusCurrState == STATE_READY & |RW) |
+  // communication to cache
-                          (BusCurrState == STATE_CAPTURE) |
+  assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount);
-                          (BusCurrState == STATE_DELAY);
-
-  assign CacheBusAck = (CacheAccess & HREADY & WordCountFlag);
-
   assign SelBusWord = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) |
 						   (BusCurrState == STATE_CAPTURE & RW[0]) |
                            (BusCurrState == STATE_CACHE_EVICT);

pipelined/src/cache/AHBCachedp.sv

@@ -59,7 +59,6 @@ module AHBCachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   input logic [`PA_BITS-1:0]  PAdr,
   input logic [1:0]           RW,
   input logic                 CPUBusy,
-  input logic                 Cacheable,
   input logic [2:0]           Funct3,
   output logic                SelBusWord,
   output logic                BusStall,
@@ -85,6 +84,6 @@ module AHBCachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
 
   AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
     .HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
-    .CacheRW, .CacheBusAck, .Cacheable, .SelUncachedAdr, .WordCount, .WordCountDelayed,
+    .CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
 	.HREADY, .HTRANS, .HWRITE, .HBURST);
 endmodule

pipelined/src/ifu/ifu.sv

@@ -235,7 +235,7 @@ module ifu (
             .WordCount(), .SelUncachedAdr, .SelBusWord(),
               .CacheBusAck(ICacheBusAck), 
             .FetchBuffer, .PAdr(PCPF),
-            .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF}), .CPUBusy, .Cacheable(CacheableF),
+            .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF}), .CPUBusy,
             .BusStall, .BusCommitted());
 
       mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),

pipelined/src/lsu/lsu.sv

@@ -262,7 +262,7 @@ module lsu (
         .WordCount, .SelBusWord,
         .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheRW({DCacheFetchLine, DCacheWriteLine} & ~{IgnoreRequest, IgnoreRequest}),
         .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM),
-        .SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM}), .CPUBusy, .Cacheable(CacheableM),
+        .SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM}), .CPUBusy,
         .BusStall, .BusCommitted(BusCommittedM));
 
       mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }),