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change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe

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the byte write-enables were always tied high, so we can use
RAM without byte-enable to increase coverage.
This commit is contained in:
Alec Vercruysse 2023-04-05 11:36:02 -07:00
parent 782feb6161
commit 81125d3180
1 changed files with 2 additions and 2 deletions
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4
src/cache/cacheway.sv vendored
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@ -107,8 +107,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
// Tag Array
/////////////////////////////////////////////////////////////////////////////////////////////
ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
.addr(CacheSet), .dout(ReadTag), .bwe('1),
ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
.addr(CacheSet), .dout(ReadTag),
.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
// AND portion of distributed tag multiplexer