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							@ -3,3 +3,4 @@
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#vsim work files to ignore
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transcript
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vsim.wlf
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wally-pipelined/wlft*
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@ -25,6 +25,33 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
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      reset <= 1; # 22; reset <= 0;
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    end
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  // read instr trace file
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  integer data_file, scan_file;
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  integer read_data;
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  initial begin
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    data_file = $fopen("busybear-testgen/parsed.txt", "r");
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    if (data_file == 0) begin
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      $display("file couldn't be opened");
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      $stop;
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    end 
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   //   scan_file = $fscanf(data_file, "%x\n", read_data);
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   //   $display("%x", read_data);
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   //   scan_file = $fscanf(data_file, "%s\n", read_data);
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   //   $display("%s", read_data);
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   //   //if (!$feof(data_file)) begin
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   //   //  $display(read_data);
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   //   //end
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   // end
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  end
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  always @(PCF) begin
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    //$display("%x", PCF);
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    scan_file = $fscanf(data_file, "%x\n", InstrF);
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    //$display("%x", InstrF);
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  end
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  // generate clock to sequence tests
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  always
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    begin
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