Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

declare memread signal

Browse Source
This commit is contained in:
bbracker 2021-04-05 08:13:01 -04:00
parent eca92041e9
commit 80a67dc906
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
wally-pipelined/src/uncore/plic.sv
View File

@ -49,7 +49,7 @@ module plic (
localparam N=`PLIC_NUM_SRC; // should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec
logic memwrite, initTrans;
logic memwrite, memread, initTrans;
logic [27:0] entry, entryd;
logic [31:0] Din, Dout;
logic [N:1] requests;
@ -167,7 +167,7 @@ module plic (
`endif
// or temporarily connect them to nothing
assign requests[3:1] = 3'b0;
// pending updates
// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
assign nextIntPending = (intPending | (requests & ~intInProgress)) // requests should raise intPending except when their service routine is already in progress