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declare memread signal

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bbracker 2021-04-05 08:13:01 -04:00
parent eca92041e9
commit 80a67dc906
1 changed files with 2 additions and 2 deletions
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wally-pipelined/src/uncore/plic.sv
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@ -49,7 +49,7 @@ module plic (
localparam N=`PLIC_NUM_SRC; // should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec
logic memwrite, initTrans;
logic memwrite, memread, initTrans;
logic [27:0] entry, entryd;
logic [31:0] Din, Dout;
logic [N:1] requests;