Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

Browse Source
This commit is contained in:
Thomas Fleming 2021-04-22 13:20:12 -04:00
commit 805ac5dbd7
3 changed files with 54 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wally-pipelined/config/rv32ic/wally-config.vh
View File

@ -95,6 +95,8 @@
// Interrupt configuration // Interrupt configuration
`define PLIC_NUM_SRC 4 `define PLIC_NUM_SRC 4
// comment out the following if >=32 sources
`define PLIC_NUM_SRC_LT_32
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4 `define PLIC_UART_ID 4

2
wally-pipelined/config/rv64ic/wally-config.vh
View File

@ -96,6 +96,8 @@
// Interrupt configuration // Interrupt configuration
`define PLIC_NUM_SRC 4 `define PLIC_NUM_SRC 4
// comment out the following if >=32 sources
`define PLIC_NUM_SRC_LT_32
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define PLIC_UART_ID 4 `define PLIC_UART_ID 4

115
wally-pipelined/src/uncore/plic.sv
View File

@ -12,8 +12,6 @@
// *** Big questions: // *** Big questions:
// Do we detect requests as level-triggered or edge-trigged? // Do we detect requests as level-triggered or edge-trigged?
// If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests? // If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests?
// Should PLIC also output SEIP or just MEIP?
// MEIP is the same as ExtIntM, right?
// //
// A component of the Wally configurable RISC-V project. // A component of the Wally configurable RISC-V project.
// //
@ -65,7 +63,9 @@ module plic (
logic [N:1] pendingRequestsAtMaxP; logic [N:1] pendingRequestsAtMaxP;
logic [7:1] threshMask; logic [7:1] threshMask;
// =======
// AHB I/O // AHB I/O
// =======
assign entry = {HADDR[27:2],2'b0}; assign entry = {HADDR[27:2],2'b0};
assign initTrans = HREADY & HSELPLIC & (HTRANS != 2'b00); assign initTrans = HREADY & HSELPLIC & (HTRANS != 2'b00);
assign memread = initTrans & ~HWRITE; assign memread = initTrans & ~HWRITE;
@ -77,7 +77,8 @@ module plic (
// account for subword read/write circuitry // account for subword read/write circuitry
// -- Note PLIC registers are 32 bits no matter what; access them with LW SW. // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
generate // *** add ld, sd functionality // *** add ld, sd functionality
generate
if (`XLEN == 64) begin if (`XLEN == 64) begin
always_comb always_comb
if (entryd[2]) begin if (entryd[2]) begin
@ -95,71 +96,54 @@ module plic (
end end
endgenerate endgenerate
// register interface // ==================
genvar i; // Register Interface
generate // ==================
// priority registers always @(posedge HCLK,negedge HRESETn) begin
for (i=1; i<=N; i=i+1) // resetting
always @(posedge HCLK,negedge HRESETn) if (~HRESETn) begin
if (~HRESETn) intPriority <= #1 '{default:3'b0}; // *** does this initialization synthesize cleanly?
intPriority[i] <= 3'b0; intEn <= #1 {N{1'b0}};
else begin intThreshold <= #1 3'b0;
if (entry == 28'hc000000+4*i) // *** make sure this does not synthesize into N 28-bit equality comparators; we want something more decoder-ish intInProgress <= #1 {N{1'b0}};
Dout <= #1 {{(`XLEN-3){1'b0}},intPriority[i]}; // writing
if ((entryd == 28'hc000000+4*i) && memwrite) end else if (memwrite)
intPriority[i] <= #1 Din[2:0]; casez(entryd)
end 28'hc0000??: intPriority[entryd[7:2]] <= #1 Din[2:0];
`ifdef PLIC_NUM_SRC_LT_32
// pending and enable registers 28'hc002000: intEn[N:1] <= #1 Din[N:1];
if (N<32) `endif
always @(posedge HCLK,negedge HRESETn) `ifndef PLIC_NUM_SRC_LT_32
if (~HRESETn) 28'hc002000: intEn[31:1] <= #1 Din[31:1];
intEn <= {N{1'b0}}; 28'hc002004: intEn[N:32] <= #1 Din[31:0];
else begin `endif
if (entry == 28'hc001000) 28'hc200000: intThreshold[2:0] <= #1 Din[2:0];
Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0}; 28'hc200004: intInProgress <= #1 intInProgress & ~(1'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
if (entry == 28'hc002000) endcase
Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0}; // reading
if ((entryd == 28'hc002000) && memwrite) if (memread)
intEn[N:1] <= #1 Din[N:1]; casez(entry)
end 28'hc0000??: Dout <= #1 {{(`XLEN-3){1'b0}},intPriority[entry[7:2]]};
else // N>=32 `ifdef PLIC_NUM_SRC_LT_32
always @(posedge HCLK,negedge HRESETn) 28'hc001000: Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0};
if (~HRESETn) 28'hc002000: Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0};
intEn <= {N{1'b0}}; `endif
else begin `ifndef PLIC_NUM_SRC_LT_32
if (entry == 28'hc001000) 28'hc001000: Dout <= #1 {intPending[31:1],1'b0};
Dout <= #1 {intPending[31:1],1'b0}; 28'hc001004: Dout <= #1 {{(63-N){1'b0}},intPending[N:32]};
if (entry == 28'hc001004) 28'hc002000: Dout <= #1 {intEn[31:1],1'b0};
Dout <= #1 {{(63-N){1'b0}},intPending[N:32]}; 28'hc002004: Dout <= #1 {{(63-N){1'b0}},intEn[N:32]};
if (entry == 28'hc002000) `endif
Dout <= #1 {intEn[31:1],1'b0}; 28'hc200000: Dout <= #1 {29'b0,intThreshold[2:0]};
if (entry == 28'hc002004) 28'hc200004: begin
Dout <= #1 {{(63-N){1'b0}},intEn[N:32]};
if ((entryd == 28'hc002000) && memwrite)
intEn[31:1] <= #1 Din[31:1];
if ((entryd == 28'hc002004) && memwrite)
intEn[N:32] <= #1 Din[31:0];
end
// threshold and claim/complete registers
always @(posedge HCLK, negedge HRESETn)
if (~HRESETn) begin
intThreshold<=3'b0;
intInProgress <= {N{1'b0}};
end else begin
if (entry == 28'hc200000)
Dout <= #1 {29'b0,intThreshold[2:0]};
if ((entryd == 28'hc200000) && memwrite)
intThreshold[2:0] <= #1 Din[2:0];
if ((entry == 28'hc200004) && memread) begin // check for memread because reading claim reg. has side effects
Dout <= #1 {26'b0,intClaim}; Dout <= #1 {26'b0,intClaim};
intInProgress <= #1 intInProgress | (1'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed intInProgress <= #1 intInProgress | (1'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
end end
if ((entryd == 28'hc200004) && memwrite) default: Dout <= #1 32'hdeadbeef; // invalid access
intInProgress <= #1 intInProgress & ~(1'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion endcase
end else
endgenerate Dout <= #1 32'h0;
end
// connect sources to requests // connect sources to requests
always_comb begin always_comb begin
@ -179,6 +163,7 @@ module plic (
flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending); flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
// pending array - indexed by priority_lvl x source_ID // pending array - indexed by priority_lvl x source_ID
genvar i;
generate generate
for (i=1; i<=N; i=i+1) begin for (i=1; i<=N; i=i+1) begin
// *** make sure that this synthesizes into N decoders, not 7*N 3-bit equality comparators (right?) // *** make sure that this synthesizes into N decoders, not 7*N 3-bit equality comparators (right?)