From 37e74648a9b76a72accf3ff434c45f136b91efde Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Mon, 23 May 2022 23:07:27 +0000 Subject: [PATCH 01/28] added exponents to srt divider --- pipelined/srt/Makefile | 8 +- pipelined/srt/srt.sv | 18 + pipelined/srt/testbench.sv | 26 +- pipelined/srt/testgen | Bin 13088 -> 0 bytes pipelined/srt/testvectors | 1078 ++++++++++-------------------------- 5 files changed, 328 insertions(+), 802 deletions(-) delete mode 100755 pipelined/srt/testgen diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile index 73a0b75fa..f8343f584 100644 --- a/pipelined/srt/Makefile +++ b/pipelined/srt/Makefile @@ -4,4 +4,10 @@ sqrttestgen: sqrttestgen.c gcc sqrttestgen.c -lm -o sqrttestgen testgen: testgen.c - gcc testgen.c -lm -o testgen + gcc -lm -o testgen testgen.c + ./testgen + + +exptestgen: exptestgen.c + gcc -lm -o exptestgen exptestgen.c + ./exptestgen diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index 044bac9c1..52e087c9a 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -37,6 +37,7 @@ module srt #(parameter Nf=52) ( input logic Flush, // *** multiple pipe stages // Floating Point Inputs // later add exponents, signs, special cases + input logic [`NE-1:0] XExp, YExp, input logic [Nf-1:0] SrcXFrac, SrcYFrac, input logic [`XLEN-1:0] SrcA, SrcB, input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit @@ -45,6 +46,7 @@ module srt #(parameter Nf=52) ( input logic Int, // Choose integer inputss input logic Sqrt, // perform square root, not divide output logic [Nf-1:0] Quot, Rem, // *** later handle integers + output logic [`NE-1:0] rExp, output logic [3:0] Flags ); @@ -78,6 +80,8 @@ module srt #(parameter Nf=52) ( // Partial Product Generation csa csa(WS, WC, Dsel, qp, WSA, WCA); + expcalc expcalc(.XExp, .YExp, .rExp); + srtpostproc postproc(rp, rm, Quot); endmodule @@ -247,6 +251,20 @@ module csa #(parameter N=56) ( (in2[54:0] & in3[54:0]), cin}; endmodule + +////////////// +// expcalc // +////////////// + +module expcalc( + input logic [`NE-1:0] XExp, YExp, + output logic [`NE-1:0] rExp +); + + assign rExp = XExp - YExp + `BIAS; + +endmodule + ////////////// // finaladd // ////////////// diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 0af3821ec..0958bf72c 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -40,30 +40,32 @@ module testbench; logic clk; logic req; logic done; - logic [51:0] a; - logic [51:0] b; + logic [62:0] a; + logic [62:0] b; logic [51:0] r; logic [54:0] rp, rm; // positive quotient digits // Test parameters parameter MEM_SIZE = 40000; - parameter MEM_WIDTH = 52+52+52; + parameter MEM_WIDTH = 64+64+64; - `define memr 51:0 - `define memb 103:52 - `define mema 155:104 + `define memr 62:0 + `define memb 126:64 + `define mema 190:128 // Test logicisters logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a // bit field of an array - logic [51:0] correctr, nextr, diffn, diffp; + logic [62:0] correctr, nextr, diffn, diffp; + logic [10:0] rExp; integer testnum, errors; // Divider srt #(52) srt(.clk, .Start(req), .Stall(1'b0), .Flush(1'b0), - .SrcXFrac(a), .SrcYFrac(b), + .XExp(a[62:52]), .YExp(b[62:52]), .rExp, + .SrcXFrac(a[51:0]), .SrcYFrac(b[51:0]), .SrcA('0), .SrcB('0), .Fmt(2'b00), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), .Quot(r), .Rem(), .Flags()); @@ -100,12 +102,12 @@ module testbench; if (done) begin req <= #5 1; - diffp = correctr - r; - diffn = r - correctr; - if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp + diffp = correctr[51:0] - r; + diffn = r - correctr[51:0]; + if ((rExp === correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp begin errors = errors+1; - $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); + $display("result was %h_%h, should be %h %h %h\n", rExp, r, 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+4032000000000000_410c71c71c71c71c_3f24400000000000 +4041000000000000_410c71c71c71c71c_3f33200000000000 +405c000000000000_410c71c71c71c71c_3f4f800000000000 +406e000000000000_410c71c71c71c71c_3f50e00000000000 +407ffff583a53b8e_410c71c71c71c71c_3f61fffa1a0cf180 +408199999999999a_410c71c71c71c71c_3f73ccccccccccce +4093333333333333_410c71c71c71c71c_3f8599999999999a +40a028f5c28f5c29_410c71c71c71c71c_3f922e147ae147ae +40b004189374bc6a_410c71c71c71c71c_3fa2049ba5e353f8 +40c00068db8bac71_410c71c71c71c71c_3fb20075f6fd21ff +40dd1745d1745d17_410c71c71c71c71c_3fc05d1745d1745d +40e5555555555555_410c71c71c71c71c_3fd8000000000000 +40f999999999999a_410c71c71c71c71c_3fecccccccccccce +410c71c71c71c71c_410c71c71c71c71c_3ff0000000000000 From cd9f0cd6bd6317bca2268dee5601840009673fbf Mon Sep 17 00:00:00 2001 From: slmnemo Date: Mon, 23 May 2022 19:24:28 -0700 Subject: [PATCH 02/28] fixed a comment spelling typo --- pipelined/regression/wally-pipelined-batch.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index 85d8513ec..bdfa326de 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -51,7 +51,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf #vsim -coverage -lib work_$2 workopt_$2 - # power add generates the logging necessary for saif generation. + # power add generates the logging necessary for said generation. # power add -r /dut/core/* run -all # power off -r /dut/core/* From 7d1448d2ad9b4f888143edc90cc571d6ac708ff0 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Wed, 25 May 2022 06:44:22 +0000 Subject: [PATCH 03/28] added support for tsmc28, fixed ff modules/analysis for timing --- pipelined/src/ppa/ppa.sv | 242 +++++++++++++++++++++++++------------ synthDC/.synopsys_dc.setup | 5 + synthDC/ppaAnalyze.py | 47 +++++-- synthDC/ppaSynth.py | 8 +- synthDC/scripts/synth.tcl | 8 ++ 5 files changed, 219 insertions(+), 91 deletions(-) diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index a08e4ff59..61840a92c 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -126,6 +126,16 @@ module ppa_mult_128 #(parameter WIDTH=128) ( assign y = a * b; endmodule +module ppa_alu_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] ALUControl, + input logic [2:0] Funct3, + output logic [WIDTH-1:0] Result, + output logic [WIDTH-1:0] Sum); + + ppa_alu #(WIDTH) alu (.*); +endmodule + module ppa_alu_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, B, input logic [2:0] ALUControl, @@ -133,7 +143,7 @@ module ppa_alu_16 #(parameter WIDTH=16) ( output logic [WIDTH-1:0] Result, output logic [WIDTH-1:0] Sum); - ppa_alu #(WIDTH) alu_16 (.*); + ppa_alu #(WIDTH) alu (.*); endmodule module ppa_alu_32 #(parameter WIDTH=32) ( @@ -143,7 +153,7 @@ module ppa_alu_32 #(parameter WIDTH=32) ( output logic [WIDTH-1:0] Result, output logic [WIDTH-1:0] Sum); - ppa_alu #(WIDTH) alu_32 (.*); + ppa_alu #(WIDTH) alu (.*); endmodule module ppa_alu_64 #(parameter WIDTH=64) ( @@ -153,7 +163,17 @@ module ppa_alu_64 #(parameter WIDTH=64) ( output logic [WIDTH-1:0] Result, output logic [WIDTH-1:0] Sum); - ppa_alu #(WIDTH) alu_64 (.*); + ppa_alu #(WIDTH) alu (.*); +endmodule + +module ppa_alu_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] ALUControl, + input logic [2:0] Funct3, + output logic [WIDTH-1:0] Result, + output logic [WIDTH-1:0] Sum); + + ppa_alu #(WIDTH) alu (.*); endmodule module ppa_alu #(parameter WIDTH=32) ( @@ -209,9 +229,11 @@ module ppa_alu #(parameter WIDTH=32) ( 3'b111: FullResult = A & B; // and endcase - // support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits - if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign Result = FullResult; + assign Result = FullResult; + // not using W64 so it has the same architecture regardless of width + // // support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits + // if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + // else assign Result = FullResult; endmodule module ppa_shiftleft_8 #(parameter WIDTH=8) ( @@ -313,29 +335,35 @@ module ppa_shifter #(parameter WIDTH=32) ( // For RV64, 32 and 64-bit shifts are needed, with sign extension. // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (WIDTH == 64 | WIDTH ==128) begin:shifter // RV64 or 128 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {{WIDTH{1'b0}}, {WIDTH/2 -1{A[WIDTH/2 -1]}}, A[WIDTH/2 -1:0]}; - else z = {{WIDTH*3/2-1{1'b0}}, A[WIDTH/2 -1:0]}; - else z = {{WIDTH/2{1'b0}}, A[WIDTH/2 -1:0], {WIDTH-1{1'b0}}}; - end else begin - if (Right) - if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; - else z = {{WIDTH-1{1'b0}}, A}; - else z = {A, {WIDTH-1{1'b0}}}; - end - assign amttrunc = W64 ? {1'b0, Amt[$clog2(WIDTH)-2:0]} : Amt; // 32 or 64-bit shift - end else begin:shifter // RV32 or less - always_comb // funnel mux + // if (WIDTH == 64 | WIDTH ==128) begin:shifter // RV64 or 128 + // always_comb // funnel mux + // if (W64) begin // 32-bit shifts + // if (Right) + // if (Arith) z = {{WIDTH{1'b0}}, {WIDTH/2 -1{A[WIDTH/2 -1]}}, A[WIDTH/2 -1:0]}; + // else z = {{WIDTH*3/2-1{1'b0}}, A[WIDTH/2 -1:0]}; + // else z = {{WIDTH/2{1'b0}}, A[WIDTH/2 -1:0], {WIDTH-1{1'b0}}}; + // end else begin + // if (Right) + // if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + // else z = {{WIDTH-1{1'b0}}, A}; + // else z = {A, {WIDTH-1{1'b0}}}; + // end + // assign amttrunc = W64 ? {1'b0, Amt[$clog2(WIDTH)-2:0]} : Amt; // 32 or 64-bit shift + // end else begin:shifter // RV32 or less + // always_comb // funnel mux + // if (Right) + // if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + // else z = {{WIDTH-1{1'b0}}, A}; + // else z = {A, {WIDTH-1{1'b0}}}; + // assign amttrunc = Amt; // shift amount + // end + + always_comb // funnel mux if (Right) if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; else z = {{WIDTH-1{1'b0}}, A}; else z = {A, {WIDTH-1{1'b0}}}; assign amttrunc = Amt; // shift amount - end - // opposite offset for right shfits assign offset = Right ? amttrunc : ~amttrunc; @@ -538,7 +566,7 @@ endmodule // *** some way to express data-critical inputs -module ppa_flop_8 #(parameter WIDTH = 8) ( +module ppa_flop #(parameter WIDTH = 8) ( input logic clk, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); @@ -547,13 +575,26 @@ module ppa_flop_8 #(parameter WIDTH = 8) ( q <= #1 d; endmodule +module ppa_flop_8 #(parameter WIDTH = 8) ( + input logic clk, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + logic [WIDTH-1:0] q1; + + ppa_flop #(WIDTH) f1(clk, d, q1); + ppa_flop #(WIDTH) f2(clk, q1, q); +endmodule + module ppa_flop_16 #(parameter WIDTH = 16) ( input logic clk, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flop #(WIDTH) f1(clk, d, q1); + ppa_flop #(WIDTH) f2(clk, q1, q); endmodule module ppa_flop_32 #(parameter WIDTH = 32) ( @@ -561,8 +602,10 @@ module ppa_flop_32 #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flop #(WIDTH) f1(clk, d, q1); + ppa_flop #(WIDTH) f2(clk, q1, q); endmodule module ppa_flop_64 #(parameter WIDTH = 64) ( @@ -570,8 +613,10 @@ module ppa_flop_64 #(parameter WIDTH = 64) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flop #(WIDTH) f1(clk, d, q1); + ppa_flop #(WIDTH) f2(clk, q1, q); endmodule module ppa_flop_128 #(parameter WIDTH = 128) ( @@ -579,8 +624,20 @@ module ppa_flop_128 #(parameter WIDTH = 128) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); + logic [WIDTH-1:0] q1; + + ppa_flop #(WIDTH) f1(clk, d, q1); + ppa_flop #(WIDTH) f2(clk, q1, q); +endmodule + +module ppa_flopr #(parameter WIDTH = 8) ( + input logic clk, reset, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + always_ff @(posedge clk) - q <= #1 d; + if (reset) q <= #1 0; + else q <= #1 d; endmodule module ppa_flopr_8 #(parameter WIDTH = 8) ( @@ -588,9 +645,10 @@ module ppa_flopr_8 #(parameter WIDTH = 8) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - if (reset) q <= #1 0; - else q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flopr #(WIDTH) f1(clk, reset, d, q1); + ppa_flopr #(WIDTH) f2(clk, reset, q1, q); endmodule module ppa_flopr_16 #(parameter WIDTH = 16) ( @@ -598,9 +656,10 @@ module ppa_flopr_16 #(parameter WIDTH = 16) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - if (reset) q <= #1 0; - else q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flopr #(WIDTH) f1(clk, reset, d, q1); + ppa_flopr #(WIDTH) f2(clk, reset, q1, q); endmodule module ppa_flopr_32 #(parameter WIDTH = 32) ( @@ -608,9 +667,10 @@ module ppa_flopr_32 #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - if (reset) q <= #1 0; - else q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flopr #(WIDTH) f1(clk, reset, d, q1); + ppa_flopr #(WIDTH) f2(clk, reset, q1, q); endmodule module ppa_flopr_64 #(parameter WIDTH = 64) ( @@ -618,9 +678,10 @@ module ppa_flopr_64 #(parameter WIDTH = 64) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - if (reset) q <= #1 0; - else q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flopr #(WIDTH) f1(clk, reset, d, q1); + ppa_flopr #(WIDTH) f2(clk, reset, q1, q); endmodule module ppa_flopr_128 #(parameter WIDTH = 128) ( @@ -628,7 +689,18 @@ module ppa_flopr_128 #(parameter WIDTH = 128) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) + logic [WIDTH-1:0] q1; + + ppa_flopr #(WIDTH) f1(clk, reset, d, q1); + ppa_flopr #(WIDTH) f2(clk, reset, q1, q); +endmodule + +module ppa_floprasync #(parameter WIDTH = 8) ( + input logic clk, reset, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk or posedge reset) if (reset) q <= #1 0; else q <= #1 d; endmodule @@ -638,9 +710,10 @@ module ppa_floprasync_8 #(parameter WIDTH = 8) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk or posedge reset) - if (reset) q <= #1 0; - else q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_floprasync #(WIDTH) f1(clk, reset, d, q1); + ppa_floprasync #(WIDTH) f2(clk, reset, q1, q); endmodule module ppa_floprasync_16 #(parameter WIDTH = 16) ( @@ -648,9 +721,10 @@ module ppa_floprasync_16 #(parameter WIDTH = 16) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk or posedge reset) - if (reset) q <= #1 0; - else q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_floprasync #(WIDTH) f1(clk, reset, d, q1); + ppa_floprasync #(WIDTH) f2(clk, reset, q1, q); endmodule module ppa_floprasync_32 #(parameter WIDTH = 32) ( @@ -658,9 +732,10 @@ module ppa_floprasync_32 #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk or posedge reset) - if (reset) q <= #1 0; - else q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_floprasync #(WIDTH) f1(clk, reset, d, q1); + ppa_floprasync #(WIDTH) f2(clk, reset, q1, q); endmodule module ppa_floprasync_64 #(parameter WIDTH = 64) ( @@ -668,9 +743,10 @@ module ppa_floprasync_64 #(parameter WIDTH = 64) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk or posedge reset) - if (reset) q <= #1 0; - else q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_floprasync #(WIDTH) f1(clk, reset, d, q1); + ppa_floprasync #(WIDTH) f2(clk, reset, q1, q); endmodule module ppa_floprasync_128 #(parameter WIDTH = 128) ( @@ -678,9 +754,20 @@ module ppa_floprasync_128 #(parameter WIDTH = 128) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk or posedge reset) - if (reset) q <= #1 0; - else q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_floprasync #(WIDTH) f1(clk, reset, d, q1); + ppa_floprasync #(WIDTH) f2(clk, reset, q1, q); +endmodule + +module ppa_flopenr #(parameter WIDTH = 8) ( + input logic clk, reset, en, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk) + if (reset) q <= #1 0; + else if (en) q <= #1 d; endmodule module ppa_flopenr_8 #(parameter WIDTH = 8) ( @@ -688,9 +775,10 @@ module ppa_flopenr_8 #(parameter WIDTH = 8) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - if (reset) q <= #1 0; - else if (en) q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1); + ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q); endmodule module ppa_flopenr_16 #(parameter WIDTH = 16) ( @@ -698,9 +786,10 @@ module ppa_flopenr_16 #(parameter WIDTH = 16) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - if (reset) q <= #1 0; - else if (en) q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1); + ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q); endmodule module ppa_flopenr_32 #(parameter WIDTH = 32) ( @@ -708,9 +797,10 @@ module ppa_flopenr_32 #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - if (reset) q <= #1 0; - else if (en) q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1); + ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q); endmodule module ppa_flopenr_64 #(parameter WIDTH = 64) ( @@ -718,9 +808,10 @@ module ppa_flopenr_64 #(parameter WIDTH = 64) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - if (reset) q <= #1 0; - else if (en) q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1); + ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q); endmodule module ppa_flopenr_128 #(parameter WIDTH = 128) ( @@ -728,9 +819,10 @@ module ppa_flopenr_128 #(parameter WIDTH = 128) ( input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q); - always_ff @(posedge clk) - if (reset) q <= #1 0; - else if (en) q <= #1 d; + logic [WIDTH-1:0] q1; + + ppa_flopenr #(WIDTH) f1(clk, reset, en, d, q1); + ppa_flopenr #(WIDTH) f2(clk, reset, en, q1, q); endmodule module ppa_csa_8 #(parameter WIDTH = 8) ( diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 95b39b13f..ddb62533e 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -17,6 +17,9 @@ if {$tech == "sky130"} { } elseif {$tech == "sky90"} { set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib lappend search_path $s9lib +} elseif {$tech == "tsmc28"} { + set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a + lappend search_path $s10lib } # Synthetic libraries @@ -30,6 +33,8 @@ if {$tech == "sky130"} { lappend target_library $s8lib/sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db } elseif {$tech == "sky90"} { lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db +} elseif {$tech == "tsmc28"} { + lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db } # Set Link Library diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index 101e278f4..0200d316d 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -66,6 +66,7 @@ def getVals(module, var, freq=None): elif (var == 'area'): ind = 4 units = " (sq microns)" + scale = 2 elif (var == 'lpower'): ind = 5 units = " (nW)" @@ -92,6 +93,9 @@ def getVals(module, var, freq=None): m = oneSynth[3] met = oneSynth[ind] metric += [met] + + if ('flop' in module) & (var == 'area'): + metric = [m/2 for m in metric] # since two flops in each module return widths, metric, units def writeCSV(): @@ -250,13 +254,16 @@ def freqPlot(mod, width): delaysA += [oneSynth[3]] areasA += [oneSynth[4]] - freqsV, delaysV, areasV = noOutliers(freqsV, delaysV, areasV) - freqsA, delaysA, areasA = noOutliers(freqsA, delaysA, areasA) + if ('flop' in mod): # since two flops in each module + areasA = [m/2 for m in areasA] + areasV = [m/2 for m in areasV] + + freqsA, delaysA, areasA = noOutliers(freqsA, delaysA, areasA) + freqsV, delaysV, areasV = noOutliers(freqsV, delaysV, areasV) + + adprodA, adprodV = adprodpow(areasA, delaysA, areasV, delaysV, 1) + adpowA, adpowV = adprodpow(areasA, delaysA, areasV, delaysV, 2) - adprodA = np.multiply(areasA, delaysA) - adsqA = np.multiply(adprodA, delaysA) - adprodV = np.multiply(areasV, delaysV) - adsqV = np.multiply(adprodV, delaysV) legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] @@ -268,8 +275,8 @@ def freqPlot(mod, width): ax2.scatter(freqsV, areasV, color='blue') ax3.scatter(freqsA, adprodA, color='green') ax3.scatter(freqsV, adprodV, color='blue') - ax4.scatter(freqsA, adsqA, color='green') - ax4.scatter(freqsV, adsqV, color='blue') + ax4.scatter(freqsA, adpowA, color='green') + ax4.scatter(freqsV, adpowV, color='blue') ax1.legend(handles=legend_elements) ax4.set_xlabel("Target Freq (MHz)") ax1.set_ylabel('Delay (ns)') @@ -279,19 +286,35 @@ def freqPlot(mod, width): ax1.set_title(mod + '_' + str(width)) plt.show() +def adprodpow(areasA, delaysA, areasV, delaysV, pow): + resultA = [] + resultV = [] + + for i in range(len(areasA)): + resultA += [(areasA[i])*(delaysA[i])**pow] + for i in range(len(areasV)): + resultV += [(areasV[i])*(delaysV[i])**pow] + + return resultA, resultV + def plotPPA(mod, freq=None): fig, axs = plt.subplots(2, 2) oneMetricPlot(mod, 'delay', ax=axs[0,0], fits='clg', freq=freq) oneMetricPlot(mod, 'area', ax=axs[0,1], fits='s', freq=freq) oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits='c', freq=freq) oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits='s', freq=freq) - titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " min delay" + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (min delay)" plt.suptitle(mod + titleStr) plt.show() + +# plotPPA('alu') # writeCSV() -# makeCoefTable() +# look at comparaotro 32 +# for x in ['add', 'mult', 'comparator']: +# for y in [16, 32, 64, 128]: +# freqPlot(x, y) -freqPlot('flopr', 128) +freqPlot('flop', 8) -# plotPPA('add') \ No newline at end of file +# plotPPA('alu') \ No newline at end of file diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py index 4cf045375..62c87045d 100755 --- a/synthDC/ppaSynth.py +++ b/synthDC/ppaSynth.py @@ -44,13 +44,13 @@ def getData(): allSynths = getData() arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 10, 14, 20, 40] -widths = [32, 64, 128] -modules = ['flopr'] +widths = [32, 64] +modules = ['flop', 'flopr'] tech = 'sky90' LoT = [] -# # # initial sweep to get estimate of min delay -# freqs = ['7500'] +# # # # initial sweep to get estimate of min delay +# freqs = ['10000', '15000', '20000'] # for module in modules: # for width in widths: # for freq in freqs: diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 368e45f3a..9d8395a4a 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -117,6 +117,10 @@ if {$tech == "sky130"} { } else { set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk } +} elseif {$tech == "tsmc28"} { + if ($drive == "INV") { + set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk + } } # Set input/output delay @@ -132,6 +136,10 @@ if {$tech == "sky130"} { } else { set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] } +} elseif {$tech == "tsmc28"} { + if ($drive == "INV") { + set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs] + } } # Set the wire load model From c8892f2847db3bb1021556258b22092a17bc1f4d Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Wed, 25 May 2022 13:52:20 +0000 Subject: [PATCH 04/28] ppaAnalyze: docstrings and tsmc28 plotting --- pipelined/src/ppa/ppa.sv | 91 ++++++++++--------- synthDC/ppaAnalyze.py | 187 +++++++++++++++++++++++---------------- synthDC/ppaSynth.py | 44 ++++----- 3 files changed, 180 insertions(+), 142 deletions(-) diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 61840a92c..49429e1ca 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -276,51 +276,6 @@ module ppa_shiftleft_128 #(parameter WIDTH=128) ( assign y = a << amt; endmodule -module ppa_shifter_8 #(parameter WIDTH=8) ( - input logic [WIDTH-1:0] A, - input logic [$clog2(WIDTH)-1:0] Amt, - input logic Right, Arith, W64, - output logic [WIDTH-1:0] Y); - - ppa_shifter #(WIDTH) sh (.*); -endmodule - -module ppa_shifter_16 #(parameter WIDTH=16) ( - input logic [WIDTH-1:0] A, - input logic [$clog2(WIDTH)-1:0] Amt, - input logic Right, Arith, W64, - output logic [WIDTH-1:0] Y); - - ppa_shifter #(WIDTH) sh (.*); -endmodule - -module ppa_shifter_32 #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, - input logic [$clog2(WIDTH)-1:0] Amt, - input logic Right, Arith, W64, - output logic [WIDTH-1:0] Y); - - ppa_shifter #(WIDTH) sh (.*); -endmodule - -module ppa_shifter_64 #(parameter WIDTH=64) ( - input logic [WIDTH-1:0] A, - input logic [$clog2(WIDTH)-1:0] Amt, - input logic Right, Arith, W64, - output logic [WIDTH-1:0] Y); - - ppa_shifter #(WIDTH) sh (.*); -endmodule - -module ppa_shifter_128 #(parameter WIDTH=128) ( - input logic [WIDTH-1:0] A, - input logic [$clog2(WIDTH)-1:0] Amt, - input logic Right, Arith, W64, - output logic [WIDTH-1:0] Y); - - ppa_shifter #(WIDTH) sh (.*); -endmodule - module ppa_shifter #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -373,7 +328,51 @@ module ppa_shifter #(parameter WIDTH=32) ( assign Y = zshift[WIDTH-1:0]; endmodule -// just report one hot + // module ppa_shifter_8 #(parameter WIDTH=8) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + + // module ppa_shifter_16 #(parameter WIDTH=16) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + + // module ppa_shifter_32 #(parameter WIDTH=32) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + + // module ppa_shifter_64 #(parameter WIDTH=64) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + + // module ppa_shifter_128 #(parameter WIDTH=128) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + module ppa_prioritythermometer #(parameter N = 8) ( input logic [N-1:0] a, output logic [N-1:0] y); diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index 0200d316d..935564afc 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -2,6 +2,7 @@ # Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22 from distutils.log import error +from operator import index from statistics import median import subprocess import statistics @@ -12,13 +13,16 @@ import matplotlib.lines as lines import numpy as np -def getData(mod=None, width=None): +def getData(tech, mod=None, width=None): + ''' returns a list of lists + each list contains results of one synthesis that matches the input specs + ''' specStr = '' if mod != None: specStr = mod if width != None: specStr += ('_'+str(width)) - specStr += '*' + specStr += '*{}*'.format(tech) bashCommand = "grep 'Critical Path Length' runs/ppa_{}/reports/*qor*".format(specStr) outputCPL = subprocess.check_output(['bash','-c', bashCommand]) @@ -57,8 +61,13 @@ def getData(mod=None, width=None): return allSynths -def getVals(module, var, freq=None): - allSynths = getData(mod=module) +def getVals(tech, module, var, freq=None): + ''' for a specified tech, module, and variable/metric + returns a list of widths and the corresponding values for that metric with the appropriate units + works at a specified target frequency or if none is given, uses the synthesis with the min delay for each width + ''' + + allSynths = getData(tech, mod=module) if (var == 'delay'): ind = 3 @@ -96,10 +105,14 @@ def getVals(module, var, freq=None): if ('flop' in module) & (var == 'area'): metric = [m/2 for m in metric] # since two flops in each module + return widths, metric, units -def writeCSV(): - allSynths = getData() +def writeCSV(tech): + ''' writes a CSV with one line for every available synthesis for a specified tech + each line contains the module, width, target freq, and resulting metrics + ''' + allSynths = getData(tech) file = open("ppaData.csv", "w") writer = csv.writer(file) writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)']) @@ -109,7 +122,10 @@ def writeCSV(): file.close() -def genLegend(fits, coefs, module, r2): +def genLegend(fits, coefs, r2, tech): + ''' generates a list of two legend elements + labels line with fit equation and dots with tech and r squared of the fit + ''' coefsr = [str(round(c, 3)) for c in coefs] @@ -131,26 +147,18 @@ def genLegend(fits, coefs, module, r2): eq += " + " + coefsr[ind] + "*Nlog2(N)" ind += 1 - legend_elements = [lines.Line2D([0], [0], color='orange', label=eq), - lines.Line2D([0], [0], color='steelblue', ls='', marker='o', label=' R^2='+ str(round(r2, 4)))] + c = 'blue' if (tech == 'sky90') else 'green' + legend_elements = [lines.Line2D([0], [0], color=c, label=eq), + lines.Line2D([0], [0], color=c, ls='', marker='o', label=tech +' $R^2$='+ str(round(r2, 4)))] return legend_elements def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): + ''' module: string module name + freq: int freq (MHz) + var: string delay, area, lpower, or denergy + fits: constant, linear, square, log2, Nlog2 + plots given variable vs width for all matching syntheses with regression ''' - module: string module name - freq: int freq (MHz) - var: string delay, area, lpower, or denergy - fits: constant, linear, square, log2, Nlog2 - plots chosen variable vs width for all matching syntheses with regression - ''' - widths, metric, units = getVals(module, var, freq=freq) - coefs, r2, funcArr = regress(widths, metric, fits) - - xp = np.linspace(8, 140, 200) - pred = [] - for x in xp: - y = [func(x) for func in funcArr] - pred += [sum(np.multiply(coefs, y))] if ax is None: singlePlot = True @@ -158,11 +166,17 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): else: singlePlot = False - ax.scatter(widths, metric) - ax.plot(xp, pred, color='orange') + fullLeg = [] + for tech in ['sky90', 'tsmc28']: + c = 'blue' if (tech == 'sky90') else 'green' + widths, metric, units = getVals(tech, module, var, freq=freq) + xp, pred, leg = regress(widths, metric, tech, fits) + fullLeg += leg - legend_elements = genLegend(fits, coefs, module, r2) - ax.legend(handles=legend_elements) + ax.scatter(widths, metric, color=c) + ax.plot(xp, pred, color=c) + + ax.legend(handles=fullLeg) ax.set_xticks(widths) ax.set_xlabel("Width (bits)") @@ -172,7 +186,10 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): ax.set_title(module + " (target " + str(freq) + "MHz)") plt.show() -def regress(widths, var, fits='clsgn'): +def regress(widths, var, tech, fits='clsgn'): + ''' fits a curve to the given points + returns lists of x and y values to plot that curve and legend elements with the equation + ''' funcArr = genFuncs(fits) @@ -191,9 +208,21 @@ def regress(widths, var, fits='clsgn'): except: resid = 0 r2 = 1 - resid / (y.size * y.var()) - return coefs, r2, funcArr -def makeCoefTable(): + xp = np.linspace(8, 140, 200) + pred = [] + for x in xp: + n = [func(x) for func in funcArr] + pred += [sum(np.multiply(coefs, n))] + + leg = genLegend(fits, coefs, r2, tech) + + return xp, pred, leg + +def makeCoefTable(tech): + ''' writes CSV with each line containing the coefficients for a regression fit + to a particular combination of module, metric, and target frequency + ''' file = open("ppaFitting.csv", "w") writer = csv.writer(file) writer.writerow(['Module', 'Metric', 'Freq', '1', 'N', 'N^2', 'log2(N)', 'Nlog2(N)', 'R^2']) @@ -202,7 +231,7 @@ def makeCoefTable(): for comb in [['delay', 5000], ['area', 5000], ['area', 10]]: var = comb[0] freq = comb[1] - widths, metric, units = getVals(mod, freq, var) + widths, metric, units = getVals(tech, mod, freq, var) coefs, r2, funcArr = regress(widths, metric) row = [mod] + comb + np.ndarray.tolist(coefs) + [r2] writer.writerow(row) @@ -210,6 +239,9 @@ def makeCoefTable(): file.close() def genFuncs(fits='clsgn'): + ''' helper function for regress() + returns array of functions with one for each term desired in the regression fit + ''' funcArr = [] if 'c' in fits: funcArr += [lambda x: 1] @@ -224,11 +256,17 @@ def genFuncs(fits='clsgn'): return funcArr def noOutliers(freqs, delays, areas): + ''' returns a pared down list of freqs, delays, and areas + cuts out any syntheses in which target freq isn't within 75% of the min delay target to focus on interesting area + helper function to freqPlot() + ''' f=[] d=[] a=[] + try: - med = statistics.median(freqs) + ind = delays.index(min(delays)) + med = freqs[ind] for i in range(len(freqs)): norm = freqs[i]/med if (norm > 0.25) & (norm<1.75): @@ -239,65 +277,67 @@ def noOutliers(freqs, delays, areas): return f, d, a -def freqPlot(mod, width): - allSynths = getData(mod=mod, width=width) +def freqPlot(tech, mod, width): + ''' plots delay, area, area*delay, and area*delay^2 for syntheses with specified tech, module, width + ''' + allSynths = getData(tech, mod=mod, width=width) - freqsV, delaysV, areasV, freqsA, delaysA, areasA = ([] for i in range(6)) + freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: if (mod == oneSynth[0]) & (width == oneSynth[1]): - if (1000/oneSynth[3] < oneSynth[2]): - freqsV += [oneSynth[2]] - delaysV += [oneSynth[3]] - areasV += [oneSynth[4]] - else: - freqsA += [oneSynth[2]] - delaysA += [oneSynth[3]] - areasA += [oneSynth[4]] + ind = (1000/oneSynth[3] < oneSynth[2]) # when delay is within target clock period + freqsL[ind] += [oneSynth[2]] + delaysL[ind] += [oneSynth[3]] + areasL[ind] += [oneSynth[4]] - if ('flop' in mod): # since two flops in each module - areasA = [m/2 for m in areasA] - areasV = [m/2 for m in areasV] + f, (ax1, ax2, ax3, ax4, ax5) = plt.subplots(5, 1, sharex=True) - freqsA, delaysA, areasA = noOutliers(freqsA, delaysA, areasA) - freqsV, delaysV, areasV = noOutliers(freqsV, delaysV, areasV) + for ind in [0,1]: + areas = areasL[ind] + delays = delaysL[ind] + freqs = freqsL[ind] - adprodA, adprodV = adprodpow(areasA, delaysA, areasV, delaysV, 1) - adpowA, adpowV = adprodpow(areasA, delaysA, areasV, delaysV, 2) + if ('flop' in mod): areas = [m/2 for m in areas] # since two flops in each module + freqs, delays, areas = noOutliers(freqs, delays, areas) + c = 'blue' if ind else 'green' + adprod = adprodpow(areas, delays, 2) + adpow = adprodpow(areas, delays, 3) + adpow2 = adprodpow(areas, delays, 4) + ax1.scatter(freqs, delays, color=c) + ax2.scatter(freqs, areas, color=c) + ax3.scatter(freqs, adprod, color=c) + ax4.scatter(freqs, adpow, color=c) + ax5.scatter(freqs, adpow2, color=c) legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] - f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True) - ax1.scatter(freqsA, delaysA, color='green') - ax1.scatter(freqsV, delaysV, color='blue') - ax2.scatter(freqsA, areasA, color='green') - ax2.scatter(freqsV, areasV, color='blue') - ax3.scatter(freqsA, adprodA, color='green') - ax3.scatter(freqsV, adprodV, color='blue') - ax4.scatter(freqsA, adpowA, color='green') - ax4.scatter(freqsV, adpowV, color='blue') ax1.legend(handles=legend_elements) + ax4.set_xlabel("Target Freq (MHz)") ax1.set_ylabel('Delay (ns)') ax2.set_ylabel('Area (sq microns)') ax3.set_ylabel('Area * Delay') - ax4.set_ylabel('Area * Delay^2') + ax4.set_ylabel('Area * $Delay^2$') ax1.set_title(mod + '_' + str(width)) plt.show() -def adprodpow(areasA, delaysA, areasV, delaysV, pow): - resultA = [] - resultV = [] +def adprodpow(areas, delays, pow): + ''' for each value in [areas] returns area*delay^pow + helper function for freqPlot''' + result = [] - for i in range(len(areasA)): - resultA += [(areasA[i])*(delaysA[i])**pow] - for i in range(len(areasV)): - resultV += [(areasV[i])*(delaysV[i])**pow] + for i in range(len(areas)): + result += [(areas[i])*(delays[i])**pow] - return resultA, resultV + return result def plotPPA(mod, freq=None): + ''' for the module specified, plots width vs delay, area, leakage power, and dynamic energy with fits + if no freq specified, uses the synthesis with min delay for each width + overlays data from both techs + ''' fig, axs = plt.subplots(2, 2) oneMetricPlot(mod, 'delay', ax=axs[0,0], fits='clg', freq=freq) oneMetricPlot(mod, 'area', ax=axs[0,1], fits='s', freq=freq) @@ -308,13 +348,12 @@ def plotPPA(mod, freq=None): plt.show() -# plotPPA('alu') # writeCSV() + # look at comparaotro 32 -# for x in ['add', 'mult', 'comparator']: -# for y in [16, 32, 64, 128]: -# freqPlot(x, y) -freqPlot('flop', 8) +# for x in ['add', 'mult', 'comparator', 'alu', 'csa']: +# for y in [8, 16, 32, 64, 128]: +# freqPlot('sky90', x, y) -# plotPPA('alu') \ No newline at end of file +freqPlot('sky90', 'mult', 32) \ No newline at end of file diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py index 62c87045d..949c93988 100755 --- a/synthDC/ppaSynth.py +++ b/synthDC/ppaSynth.py @@ -42,34 +42,34 @@ def getData(): return allSynths allSynths = getData() -arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 10, 14, 20, 40] +arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20, 40] -widths = [32, 64] -modules = ['flop', 'flopr'] -tech = 'sky90' +widths = [8, 16, 32, 64, 128] +modules = ['add'] +tech = 'tsmc28' LoT = [] -# # # # initial sweep to get estimate of min delay -# freqs = ['10000', '15000', '20000'] -# for module in modules: -# for width in widths: -# for freq in freqs: -# LoT += [[module, width, tech, freq]] +# # # initial sweep to get estimate of min delay +freqs = [10000, 15000, 20000] +for module in modules: + for width in widths: + for freq in freqs: + LoT += [[module, width, tech, freq]] -# thorough sweep based on estimate of min delay -for m in modules: - for w in widths: - delays = [] - for oneSynth in allSynths: - if (oneSynth[0] == m) & (oneSynth[1] == w): - delays += [oneSynth[3]] - try: f = 1000/min(delays) - except: print(m) - for freq in [str(round(f+f*x/100)) for x in arr]: - LoT += [[m, w, tech, freq]] + +# # thorough sweep based on estimate of min delay +# for m in modules: +# for w in widths: +# delays = [] +# for oneSynth in allSynths: +# if (oneSynth[0] == m) & (oneSynth[1] == w): +# delays += [oneSynth[3]] +# try: f = 1000/min(delays) +# except: print(m) +# for freq in [str(round(f+f*x/100)) for x in arr]: +# LoT += [[m, w, tech, freq]] deleteRedundant(LoT) - pool = Pool() pool.starmap(runCommand, LoT) pool.close() \ No newline at end of file From 309f85bb3827192518535a13ddfdedbc9b675df6 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Wed, 25 May 2022 20:37:54 +0000 Subject: [PATCH 05/28] major revisions to ppaAnalyze synths as namedtuples, plotting pulls from csv, support for multiple techs --- synthDC/ppaAnalyze.py | 165 ++-- synthDC/ppaData.csv | 2024 +++++++++++++++++++++++++---------------- synthDC/ppaSynth.py | 32 +- 3 files changed, 1321 insertions(+), 900 deletions(-) diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index 935564afc..d9435772f 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -1,28 +1,39 @@ #!/usr/bin/python3 # Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22 -from distutils.log import error from operator import index -from statistics import median import subprocess -import statistics import csv import re import matplotlib.pyplot as plt import matplotlib.lines as lines import numpy as np +from collections import namedtuple -def getData(tech, mod=None, width=None): - ''' returns a list of lists - each list contains results of one synthesis that matches the input specs +def synthsfromcsv(filename): + with open(filename, newline='') as csvfile: + csvreader = csv.reader(csvfile) + global allSynths + allSynths = list(csvreader) + for i in range(len(allSynths)): + for j in range(len(allSynths[0])): + try: allSynths[i][j] = int(allSynths[i][j]) + except: + try: allSynths[i][j] = float(allSynths[i][j]) + except: pass + allSynths[i] = Synth(*allSynths[i]) + +def synthsintocsv(mod=None, width=None): + ''' writes a CSV with one line for every available synthesis + each line contains the module, tech, width, target freq, and resulting metrics ''' specStr = '' if mod != None: specStr = mod if width != None: specStr += ('_'+str(width)) - specStr += '*{}*'.format(tech) + specStr += '*' bashCommand = "grep 'Critical Path Length' runs/ppa_{}/reports/*qor*".format(specStr) outputCPL = subprocess.check_output(['bash','-c', bashCommand]) @@ -41,8 +52,12 @@ def getData(tech, mod=None, width=None): wm = re.compile('ppa_\w*_\d*_qor') da = re.compile('\d*\.\d{6}') p = re.compile('\d+\.\d+[e-]*\d+') + t = re.compile('[a-zA-Z0-9]+nm') + + file = open("ppaData.csv", "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)']) - allSynths = [] for i in range(len(linesCPL)): line = linesCPL[i] mwm = wm.findall(line)[0][4:-4].split('_') @@ -51,78 +66,60 @@ def getData(tech, mod=None, width=None): area = float(da.findall(linesDA[i])[0]) mod = mwm[0] width = int(mwm[1]) + tech = t.findall(line)[0][:-2] + try: #fix + power = p.findall(linesP[i]) + lpower = float(power[2]) + denergy = float(power[1])*delay + except: + lpower = 0 + denergy = 0 - power = p.findall(linesP[i]) - lpower = float(power[2]) - denergy = float(power[1])*delay - - oneSynth = [mod, width, freq, delay, area, lpower, denergy] - allSynths += [oneSynth] - - return allSynths + writer.writerow([mod, tech, width, freq, delay, area, lpower, denergy]) + file.close() def getVals(tech, module, var, freq=None): ''' for a specified tech, module, and variable/metric - returns a list of widths and the corresponding values for that metric with the appropriate units + returns a list of values for that metric in ascending width order with the appropriate units works at a specified target frequency or if none is given, uses the synthesis with the min delay for each width ''' - - allSynths = getData(tech, mod=module) - + if (var == 'delay'): - ind = 3 units = " (ns)" elif (var == 'area'): - ind = 4 units = " (sq microns)" - scale = 2 elif (var == 'lpower'): - ind = 5 units = " (nW)" elif (var == 'denergy'): - ind = 6 units = " (pJ)" - else: - error - widths = [] + global widths metric = [] + widthL = [] if (freq != None): for oneSynth in allSynths: - if (oneSynth[2] == freq): - widths += [oneSynth[1]] - metric += [oneSynth[ind]] + if (oneSynth.freq == freq) & (oneSynth.tech == tech) & (oneSynth.module == module): + widthL += [oneSynth.width] + osdict = oneSynth._asdict() + metric += [osdict[var]] + metric = [x for _, x in sorted(zip(widthL, metric))] # ordering else: - widths = [8, 16, 32, 64, 128] for w in widths: - m = 10000 # large number to start + m = 100000 # large number to start for oneSynth in allSynths: - if (oneSynth[1] == w): - if (oneSynth[3] < m): - m = oneSynth[3] - met = oneSynth[ind] + if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == module): + if (oneSynth.delay < m): + m = oneSynth.delay + osdict = oneSynth._asdict() + met = osdict[var] metric += [met] if ('flop' in module) & (var == 'area'): metric = [m/2 for m in metric] # since two flops in each module - return widths, metric, units + return metric, units -def writeCSV(tech): - ''' writes a CSV with one line for every available synthesis for a specified tech - each line contains the module, width, target freq, and resulting metrics - ''' - allSynths = getData(tech) - file = open("ppaData.csv", "w") - writer = csv.writer(file) - writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)']) - - for one in allSynths: - writer.writerow(one) - - file.close() - -def genLegend(fits, coefs, r2, tech): +def genLegend(fits, coefs, r2, techcolor): ''' generates a list of two legend elements labels line with fit equation and dots with tech and r squared of the fit ''' @@ -147,7 +144,7 @@ def genLegend(fits, coefs, r2, tech): eq += " + " + coefsr[ind] + "*Nlog2(N)" ind += 1 - c = 'blue' if (tech == 'sky90') else 'green' + tech, c = techcolor legend_elements = [lines.Line2D([0], [0], color=c, label=eq), lines.Line2D([0], [0], color=c, ls='', marker='o', label=tech +' $R^2$='+ str(round(r2, 4)))] return legend_elements @@ -167,14 +164,17 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): singlePlot = False fullLeg = [] - for tech in ['sky90', 'tsmc28']: - c = 'blue' if (tech == 'sky90') else 'green' - widths, metric, units = getVals(tech, module, var, freq=freq) - xp, pred, leg = regress(widths, metric, tech, fits) - fullLeg += leg + global techcolors + global widths + for combo in techcolors: + tech, c = combo + metric, units = getVals(tech, module, var, freq=freq) + if len(metric) == 5: + xp, pred, leg = regress(widths, metric, combo, fits) + fullLeg += leg - ax.scatter(widths, metric, color=c) - ax.plot(xp, pred, color=c) + ax.scatter(widths, metric, color=c) + ax.plot(xp, pred, color=c) ax.legend(handles=fullLeg) @@ -183,10 +183,11 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): ax.set_ylabel(str.title(var) + units) if singlePlot: - ax.set_title(module + " (target " + str(freq) + "MHz)") + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (min delay)" + ax.set_title(module + titleStr) plt.show() -def regress(widths, var, tech, fits='clsgn'): +def regress(widths, var, techcolor, fits='clsgn'): ''' fits a curve to the given points returns lists of x and y values to plot that curve and legend elements with the equation ''' @@ -215,12 +216,13 @@ def regress(widths, var, tech, fits='clsgn'): n = [func(x) for func in funcArr] pred += [sum(np.multiply(coefs, n))] - leg = genLegend(fits, coefs, r2, tech) + leg = genLegend(fits, coefs, r2, techcolor) return xp, pred, leg def makeCoefTable(tech): - ''' writes CSV with each line containing the coefficients for a regression fit + ''' not currently in use, may salvage later + writes CSV with each line containing the coefficients for a regression fit to a particular combination of module, metric, and target frequency ''' file = open("ppaFitting.csv", "w") @@ -231,7 +233,8 @@ def makeCoefTable(tech): for comb in [['delay', 5000], ['area', 5000], ['area', 10]]: var = comb[0] freq = comb[1] - widths, metric, units = getVals(tech, mod, freq, var) + metric, units = getVals(tech, mod, freq, var) + global widths coefs, r2, funcArr = regress(widths, metric) row = [mod] + comb + np.ndarray.tolist(coefs) + [r2] writer.writerow(row) @@ -280,15 +283,14 @@ def noOutliers(freqs, delays, areas): def freqPlot(tech, mod, width): ''' plots delay, area, area*delay, and area*delay^2 for syntheses with specified tech, module, width ''' - allSynths = getData(tech, mod=mod, width=width) - + global allSynths freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: - if (mod == oneSynth[0]) & (width == oneSynth[1]): - ind = (1000/oneSynth[3] < oneSynth[2]) # when delay is within target clock period - freqsL[ind] += [oneSynth[2]] - delaysL[ind] += [oneSynth[3]] - areasL[ind] += [oneSynth[4]] + if (mod == oneSynth.module) & (width == oneSynth.width) & (tech == oneSynth.tech): + ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period + freqsL[ind] += [oneSynth.freq] + delaysL[ind] += [oneSynth.delay] + areasL[ind] += [oneSynth.area] f, (ax1, ax2, ax3, ax4, ax5) = plt.subplots(5, 1, sharex=True) @@ -347,13 +349,14 @@ def plotPPA(mod, freq=None): plt.suptitle(mod + titleStr) plt.show() +Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy") +techcolors = [['sky90', 'green'], ['tsmc28', 'blue']] +widths = [8, 16, 32, 64, 128] +synthsintocsv() -# writeCSV() +synthsfromcsv('ppaData.csv') # your csv here! -# look at comparaotro 32 - -# for x in ['add', 'mult', 'comparator', 'alu', 'csa']: -# for y in [8, 16, 32, 64, 128]: -# freqPlot('sky90', x, y) - -freqPlot('sky90', 'mult', 32) \ No newline at end of file +### examples +# oneMetricPlot('add', 'delay') +#freqPlot('sky90', 'add', 8) +#plotPPA('add') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index c7b4d9496..77f3266b1 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,803 +1,1221 @@ -Module,Width,Target Freq,Delay,Area,L Power (nW),D energy (mJ) -add,128,10,7.100851,1867.879976,465.925,0.035575263509999996 -add,128,1538,0.633294,4623.64009,632.254,0.27231642 -add,128,2051,0.486762,4951.940095,885.884,0.35630978399999996 -add,128,2359,0.423881,5520.340104,1.49,0.451433265 -add,128,2410,0.414767,5600.700103,1.57,0.456658467 -add,128,2462,0.406101,5721.240105,1.77,0.477980877 -add,128,2513,0.397913,6085.800112,2.14,0.516093161 -add,128,2564,0.436395,6456.240111,2.27,0.615753345 -add,128,2615,0.390136,6662.040117,2.45,0.6261682799999999 -add,128,2667,0.394304,7494.060127,3.58,0.76692128 -add,128,2718,0.407908,7287.280117,3.35,0.7693144879999999 -add,128,2769,0.431383,6941.340124,2.86,0.742841526 -add,128,3077,0.387515,7712.60013,2.93,0.9029099500000001 -add,128,3590,0.386891,6860.000114,2.62,0.913836542 -add,128,5000,0.389771,7007.980119,2.77,1.289752239 -add,16,10,2.032906,221.479998,55.29,0.00116892095 -add,16,2609,0.375085,405.720008,52.28,0.028731511 -add,16,3478,0.287131,443.940009,126.253,0.041921126 -add,16,4000,0.249839,551.74001,302.479,0.059711521 -add,16,4087,0.243761,503.720009,183.936,0.050946049 -add,16,4174,0.239287,549.780011,304.811,0.060061037 -add,16,4261,0.234402,607.60001,368.742,0.06680457 -add,16,4348,0.22992,610.540011,364.173,0.06575712 -add,16,4435,0.22545,666.400011,419.709,0.0789075 -add,16,4522,0.222724,820.260016,626.379,0.090871392 -add,16,4609,0.221986,815.360013,735.998,0.091680218 -add,16,4696,0.227412,866.320016,645.684,0.10392728400000001 -add,16,5000,0.228259,924.140017,641.631,0.118466421 -add,16,5217,0.22222,824.180016,601.276,0.10177676000000001 -add,16,6000,0.225754,1120.140018,1.01,0.166832206 -add,16,6087,0.226225,857.500013,678.287,0.14161685000000002 -add,32,10,4.160501,456.679995,112.161,0.00490939118 -add,32,2400,0.41509,958.440019,151.083,0.06848985 -add,32,3200,0.312424,1121.120021,296.836,0.105599312 -add,32,3680,0.271527,1465.100024,591.825,0.149882904 -add,32,3760,0.278449,1689.520028,834.387,0.18739617700000002 -add,32,3840,0.291206,1547.420027,784.112,0.177344454 -add,32,3920,0.273454,2044.280039,1.33,0.23653770999999998 -add,32,4000,0.280842,1730.680031,849.828,0.20641886999999998 -add,32,4080,0.256294,1991.360031,1.24,0.223744662 -add,32,4160,0.253175,2031.540036,1.24,0.231655125 -add,32,4240,0.268332,1829.660028,1.09,0.218958912 -add,32,4320,0.254861,1716.960028,866.723,0.199811024 -add,32,4800,0.258491,1955.100033,1.07,0.27865329800000005 -add,32,5000,0.2505,1933.540033,1.03,0.26277449999999997 -add,32,5600,0.254525,1871.800028,877.446,0.28048655 -add,32,6000,0.271774,1746.36003,955.901,0.309278812 -add,64,10,8.474034,927.079988,230.083,0.02084612364 -add,64,1818,0.538894,2114.840041,250.049,0.1347235 -add,64,2424,0.412474,2298.100044,453.413,0.175713924 -add,64,2788,0.358537,2637.180048,758.693,0.235558809 -add,64,2848,0.351091,2625.420049,698.362,0.23523097 -add,64,2909,0.343753,2800.840049,852.781,0.25368971399999996 -add,64,2970,0.337807,3412.360059,1.37,0.33003743900000004 -add,64,3030,0.331556,3202.640054,1.28,0.311331084 -add,64,3091,0.349251,3284.960053,1.35,0.34331373299999995 -add,64,3152,0.328164,3804.360061,1.89,0.39543762000000005 -add,64,3212,0.336436,3593.660062,1.72,0.38387347600000005 -add,64,3273,0.311119,3816.120062,1.96,0.39947679599999997 -add,64,3636,0.330032,3266.340054,1.22,0.407259488 -add,64,4000,0.323267,3758.300065,1.75,0.492335641 -add,64,4242,0.328234,3507.420063,1.57,0.47003108800000004 -add,64,5000,0.334061,3798.480071,2.18,0.640394937 -add,64,6000,0.328457,3749.480066,1.77,0.770560122 -add,8,10,0.940062,103.879999,24.765,0.000226554942 -add,8,5000,0.199689,197.960003,83.576,0.022564857 -comparator,128,10,0.842074,1997.240039,243.506,0.00073260438 -comparator,128,2308,0.406531,2810.640055,437.781,0.156107904 -comparator,128,3077,0.324985,2559.760047,659.43,0.17159208 -comparator,128,3538,0.282712,3158.540057,1.6,0.26490114400000003 -comparator,128,3615,0.276605,3092.880056,1.5,0.26443437999999997 -comparator,128,3692,0.270828,3380.020055,2.0,0.30170239200000004 -comparator,128,3769,0.27069,3741.640049,2.91,0.34404698999999994 -comparator,128,3846,0.273602,4038.58005,3.61,0.41751665200000004 -comparator,128,3923,0.256043,4153.240051,3.84,0.382528242 -comparator,128,4000,0.268954,4027.800041,3.66,0.44538782400000004 -comparator,128,4077,0.262622,4638.340054,5.12,0.5050221060000001 -comparator,128,4154,0.257245,4649.120047,5.1,0.5502470549999999 -comparator,128,4615,0.265848,4047.400041,3.87,0.49421143199999995 -comparator,128,5000,0.260142,5215.56005,6.0,0.964606536 -comparator,128,5385,0.267095,4787.300045,5.3,1.016830665 -comparator,16,10000,0.146177,1065.260009,1.61,0.182282719 -comparator,16,10,0.576329,252.840005,31.402,8.2991376e-05 -comparator,16,4000,0.249312,280.280005,55.248,0.0144850272 -comparator,16,5000,0.199026,313.600006,78.893,0.0170963334 -comparator,16,5333,0.186933,318.500006,100.145,0.021871161 -comparator,16,6000,0.166568,422.380007,301.506,0.04247484 -comparator,16,6133,0.16297,441.000006,363.571,0.04009062 -comparator,16,6267,0.168782,502.740008,498.843,0.053841457999999995 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+shiftleft,sky90,16,7077,0.141279,1079.960019,1.06,0.09352669799999999 +shiftleft,sky90,16,7231,0.138234,1233.820018,992.057,0.07741104 +shiftleft,sky90,16,7385,0.135404,937.860017,1.06,0.083679672 +shiftleft,sky90,16,7500,0.133331,1031.940019,874.844,0.083065213 +shiftleft,sky90,16,7538,0.132481,971.180015,940.706,0.07750138499999999 +shiftleft,sky90,16,7692,0.130257,1033.900012,1.07,0.08753270400000002 +shiftleft,sky90,16,7846,0.127358,935.900016,1.3,0.103032622 +shiftleft,sky90,16,8000,0.124837,968.240013,2.27,0.164909677 +shiftleft,sky90,16,8154,0.128748,1062.320016,4.09,0.41971847999999995 +shiftleft,sky90,16,8308,0.12432,1199.520016,319.774,0.027599040000000002 +shiftleft,sky90,16,9231,0.113513,1695.400019,2.11,0.12236701400000001 +shiftleft,sky90,32,10000,0.15971,3675.98006,2.29,0.18813837999999997 +shiftleft,sky90,32,3750,0.266551,1173.060021,2.63,0.35104766699999995 +shiftleft,sky90,32,5000,0.199946,2419.620024,2.88,0.286722564 +shiftleft,sky90,32,5750,0.173824,2582.30004,2.74,0.250654208 +shiftleft,sky90,32,5875,0.169973,2781.240046,3.13,0.284874748 +shiftleft,sky90,32,6000,0.169263,2872.380041,3.53,0.31415212800000003 +shiftleft,sky90,32,6125,0.163188,2892.960045,3.49,0.299123604 +shiftleft,sky90,32,6250,0.159977,2964.500038,4.14,0.340111102 +shiftleft,sky90,32,6375,0.159792,3330.040049,3.58,0.30999647999999996 +shiftleft,sky90,32,6500,0.158323,3294.760046,3.7,0.334853145 +shiftleft,sky90,32,6625,0.155982,3619.14005,4.46,0.44688843000000006 +shiftleft,sky90,32,6750,0.156124,3323.180043,6.06,0.9234734600000001 +shiftleft,sky90,32,7500,0.166296,3306.520048,666.022,0.061695816 +shiftleft,sky90,32,8750,0.164673,3752.420048,2.25,0.17422403400000003 +shiftleft,sky90,64,10000,0.23373,6486.620108,3.49,0.34311564 +shiftleft,sky90,64,2609,0.382901,2559.760048,2.81,0.526488875 +shiftleft,sky90,64,3478,0.287377,3864.140062,4.17,0.528198926 +shiftleft,sky90,64,4000,0.249988,4733.400082,3.95,0.4812269 +shiftleft,sky90,64,4087,0.244635,4460.960079,4.5,0.5252313449999999 +shiftleft,sky90,64,4174,0.239544,5090.120088,4.03,0.46950624 +shiftleft,sky90,64,4261,0.234657,5289.060089,5.1,0.55144395 +shiftleft,sky90,64,4348,0.23035,5490.940094,6.6,0.6104275 +shiftleft,sky90,64,4435,0.24668,5129.320094,5.97,0.67985008 +shiftleft,sky90,64,4522,0.23827,5915.280105,4.78,0.60711196 +shiftleft,sky90,64,4609,0.229176,6732.600115,6.17,0.7072371359999999 +shiftleft,sky90,64,4696,0.2291,6340.600105,5.94,0.8350695 +shiftleft,sky90,64,5000,0.239464,5848.640098,6.8,1.134101504 +shiftleft,sky90,64,5217,0.234181,6430.760098,479.939,0.074001196 +shiftleft,sky90,64,6087,0.227478,6715.940117,435.049,0.093493458 +shiftleft,sky90,64,7500,0.229635,7015.820112,328.601,0.07876480500000001 +shiftleft,sky90,8,10000,0.100846,390.040004,404.389,0.045683238 +shiftleft,sky90,8,10222,0.097799,394.940007,801.248,0.053007058 +shiftleft,sky90,8,10444,0.095384,335.160004,678.321,0.044639712 +shiftleft,sky90,8,10667,0.093734,359.660006,815.115,0.0609271 +shiftleft,sky90,8,10889,0.098154,548.800008,841.762,0.059677632 +shiftleft,sky90,8,11111,0.091007,491.960005,1.04,0.063977921 +shiftleft,sky90,8,11333,0.092595,545.860006,1.1,0.07055739 +shiftleft,sky90,8,11556,0.093322,577.220004,1.56,0.11581260200000001 +shiftleft,sky90,8,11778,0.091769,674.240011,1.35,0.10461666 +shiftleft,sky90,8,12000,0.088725,724.220008,1.13,0.09129802499999999 +shiftleft,sky90,8,13333,0.085966,939.82001,1.26,0.116226032 +shiftleft,sky90,8,15000,0.087055,827.120012,31.052,0.0032471515 +shiftleft,sky90,8,15556,0.084214,738.920012,48.381,0.0051875824 +shiftleft,sky90,8,20000,0.100914,757.540012,147.871,0.015843498 +shiftleft,sky90,8,5000,0.198975,154.840003,193.721,0.042580650000000005 +shiftleft,sky90,8,6667,0.149837,177.380003,0,0 +shiftleft,sky90,8,7500,0.132768,218.540002,0,0 +shiftleft,sky90,8,8889,0.112426,236.180002,0,0 diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py index 949c93988..4c2be07c7 100755 --- a/synthDC/ppaSynth.py +++ b/synthDC/ppaSynth.py @@ -44,30 +44,30 @@ def getData(): allSynths = getData() arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20, 40] -widths = [8, 16, 32, 64, 128] +widths = [16, 8, 32, 64, 128] modules = ['add'] tech = 'tsmc28' LoT = [] # # # initial sweep to get estimate of min delay -freqs = [10000, 15000, 20000] -for module in modules: - for width in widths: - for freq in freqs: - LoT += [[module, width, tech, freq]] +# freqs = [25000, 35000] +# for module in modules: +# for width in widths: +# for freq in freqs: +# LoT += [[module, width, tech, freq]] # # thorough sweep based on estimate of min delay -# for m in modules: -# for w in widths: -# delays = [] -# for oneSynth in allSynths: -# if (oneSynth[0] == m) & (oneSynth[1] == w): -# delays += [oneSynth[3]] -# try: f = 1000/min(delays) -# except: print(m) -# for freq in [str(round(f+f*x/100)) for x in arr]: -# LoT += [[m, w, tech, freq]] +for m in modules: + for w in widths: + delays = [] + for oneSynth in allSynths: + if (oneSynth[0] == m) & (oneSynth[1] == w): + delays += [oneSynth[3]] + try: f = 1000/min(delays) + except: print(m) + for freq in [str(round(f+f*x/100)) for x in arr]: + LoT += [[m, w, tech, freq]] deleteRedundant(LoT) pool = Pool() From c264585fe8f434b6549132bbdfa48bbcf1d08d03 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Wed, 25 May 2022 23:02:02 +0000 Subject: [PATCH 06/28] single and double conversions pass all tests --- addins/riscv-arch-test | 2 +- pipelined/config/rv64fp/wally-config.vh | 4 +- pipelined/regression/sim-wally | 2 +- pipelined/src/fpu/fctrl.sv | 122 +++++----- pipelined/src/fpu/fma.sv | 2 +- pipelined/src/fpu/fpu.sv | 22 +- pipelined/src/fpu/unpack.sv | 9 +- pipelined/testbench/testbench-fp.sv | 295 ++++++++++++++++-------- pipelined/testbench/tests-fp.vh | 12 +- tests/fp/create_vectors.sh | 160 ++++++------- 10 files changed, 372 insertions(+), 258 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..be67c99bd 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index 36cda4d91..e88b012aa 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -39,12 +39,12 @@ // MISA RISC-V configuration per specification //16 - quad 3 - double 5 - single -`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 0 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 1 +`define ZFH_SUPPORTED 0 /// Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally index 1cb461ffe..2a9fc04d6 100755 --- a/pipelined/regression/sim-wally +++ b/pipelined/regression/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally-pipelined.do rv64gc imperas64f" +vsim -do "do wally-pipelined.do rv64gc imperas64d" diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 153b97ef7..0640a544e 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -11,97 +11,97 @@ module fctrl ( output logic FDivStartD, // Start division or squareroot output logic [1:0] FResultSelD, // select result to be written to fp register output logic [2:0] FOpCtrlD, // chooses which opperation to do - specifics shown at bottom of module and in each unit - output logic [2:0] FResSelD, // select one of the results done in the memory stage + output logic [1:0] FResSelD, // select one of the results done in the memory stage output logic [1:0] FIntResSelD, // select the result that will be written to the integer register output logic FmtD, // precision - single-0 double-1 output logic [2:0] FrmD, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude output logic FWriteIntD // is the result written to the integer register ); - `define FCTRLW 14 + `define FCTRLW 13 logic [`FCTRLW-1:0] ControlsD; // FPU Instruction Decoder always_comb if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled - ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; + ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; else case(OpD) // FRegWrite_FWriteInt_FResultSel_FOpCtrl_FResSel_FIntResSel_FDivStart_IllegalFPUInstr 7'b0000111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b1_0_00_000_000_00_0_0; // flw - 3'b011: ControlsD = `FCTRLW'b1_0_00_001_000_00_0_0; // fld - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b010: ControlsD = `FCTRLW'b1_0_00_000_00_00_0_0; // flw + 3'b011: ControlsD = `FCTRLW'b1_0_00_001_00_00_0_0; // fld + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase 7'b0100111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_0_00_010_000_00_0_0; // fsw - 3'b011: ControlsD = `FCTRLW'b0_0_00_011_000_00_0_0; // fsd - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b010: ControlsD = `FCTRLW'b0_0_00_010_00_00_0_0; // fsw + 3'b011: ControlsD = `FCTRLW'b0_0_00_011_00_00_0_0; // fsd + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase - 7'b1000011: ControlsD = `FCTRLW'b1_0_01_000_000_00_0_0; // fmadd - 7'b1000111: ControlsD = `FCTRLW'b1_0_01_001_000_00_0_0; // fmsub - 7'b1001011: ControlsD = `FCTRLW'b1_0_01_010_000_00_0_0; // fnmsub - 7'b1001111: ControlsD = `FCTRLW'b1_0_01_011_000_00_0_0; // fnmadd + 7'b1000011: ControlsD = `FCTRLW'b1_0_01_000_00_00_0_0; // fmadd + 7'b1000111: ControlsD = `FCTRLW'b1_0_01_001_00_00_0_0; // fmsub + 7'b1001011: ControlsD = `FCTRLW'b1_0_01_010_00_00_0_0; // fnmsub + 7'b1001111: ControlsD = `FCTRLW'b1_0_01_011_00_00_0_0; // fnmadd 7'b1010011: casez(Funct7D) - 7'b00000??: ControlsD = `FCTRLW'b1_0_01_110_000_00_0_0; // fadd - 7'b00001??: ControlsD = `FCTRLW'b1_0_01_111_000_00_0_0; // fsub - 7'b00010??: ControlsD = `FCTRLW'b1_0_01_100_000_00_0_0; // fmul - 7'b00011??: ControlsD = `FCTRLW'b1_0_10_000_000_00_1_0; // fdiv - 7'b01011??: ControlsD = `FCTRLW'b1_0_10_001_000_00_1_0; // fsqrt + 7'b00000??: ControlsD = `FCTRLW'b1_0_01_110_00_00_0_0; // fadd + 7'b00001??: ControlsD = `FCTRLW'b1_0_01_111_00_00_0_0; // fsub + 7'b00010??: ControlsD = `FCTRLW'b1_0_01_100_00_00_0_0; // fmul + 7'b00011??: ControlsD = `FCTRLW'b1_0_10_000_00_00_1_0; // fdiv + 7'b01011??: ControlsD = `FCTRLW'b1_0_10_001_00_00_1_0; // fsqrt 7'b00100??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_11_000_001_00_0_0; // fsgnj - 3'b001: ControlsD = `FCTRLW'b1_0_11_001_001_00_0_0; // fsgnjn - 3'b010: ControlsD = `FCTRLW'b1_0_11_010_001_00_0_0; // fsgnjx - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b000: ControlsD = `FCTRLW'b1_0_11_000_01_00_0_0; // fsgnj + 3'b001: ControlsD = `FCTRLW'b1_0_11_001_01_00_0_0; // fsgnjn + 3'b010: ControlsD = `FCTRLW'b1_0_11_010_01_00_0_0; // fsgnjx + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase 7'b00101??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_11_111_010_00_0_0; // fmin - 3'b001: ControlsD = `FCTRLW'b1_0_11_101_010_00_0_0; // fmax - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b000: ControlsD = `FCTRLW'b1_0_11_111_10_00_0_0; // fmin + 3'b001: ControlsD = `FCTRLW'b1_0_11_101_10_00_0_0; // fmax + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase 7'b10100??: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_1_11_010_010_00_0_0; // feq - 3'b001: ControlsD = `FCTRLW'b0_1_11_001_010_00_0_0; // flt - 3'b000: ControlsD = `FCTRLW'b0_1_11_011_010_00_0_0; // fle - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b010: ControlsD = `FCTRLW'b0_1_11_010_10_00_0_0; // feq + 3'b001: ControlsD = `FCTRLW'b0_1_11_001_10_00_0_0; // flt + 3'b000: ControlsD = `FCTRLW'b0_1_11_011_10_00_0_0; // fle + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase - 7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_11_000_000_10_0_0; // fclass - else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_100_000_01_0_0; // fmv.x.w - else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_101_000_01_0_0; // fmv.x.d - else ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction - 7'b1101000: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b1_0_11_000_011_00_0_0; // fcvt.s.w - 2'b01: ControlsD = `FCTRLW'b1_0_11_010_011_00_0_0; // fcvt.s.wu - 2'b10: ControlsD = `FCTRLW'b1_0_11_100_011_00_0_0; // fcvt.s.l - 2'b11: ControlsD = `FCTRLW'b1_0_11_110_011_00_0_0; // fcvt.s.lu - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_11_000_00_10_0_0; // fclass + else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_100_00_01_0_0; // fmv.x.w + else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_101_00_01_0_0; // fmv.x.d + else ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction + 7'b1101000: case(Rs2D[1:0])//***reduce resSel + 2'b00: ControlsD = `FCTRLW'b1_0_11_101_11_00_0_0; // fcvt.s.w w->s + 2'b01: ControlsD = `FCTRLW'b1_0_11_100_11_00_0_0; // fcvt.s.wu wu->s + 2'b10: ControlsD = `FCTRLW'b1_0_11_111_11_00_0_0; // fcvt.s.l l->s + 2'b11: ControlsD = `FCTRLW'b1_0_11_110_11_00_0_0; // fcvt.s.lu lu->s + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase 7'b1100000: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b0_1_11_001_011_11_0_0; // fcvt.w.s - 2'b01: ControlsD = `FCTRLW'b0_1_11_011_011_11_0_0; // fcvt.wu.s - 2'b10: ControlsD = `FCTRLW'b0_1_11_101_011_11_0_0; // fcvt.l.s - 2'b11: ControlsD = `FCTRLW'b0_1_11_111_011_11_0_0; // fcvt.lu.s - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 2'b00: ControlsD = `FCTRLW'b0_1_11_001_11_11_0_0; // fcvt.w.s s->w + 2'b01: ControlsD = `FCTRLW'b0_1_11_000_11_11_0_0; // fcvt.wu.s s->wu + 2'b10: ControlsD = `FCTRLW'b0_1_11_011_11_11_0_0; // fcvt.l.s s->l + 2'b11: ControlsD = `FCTRLW'b0_1_11_010_11_11_0_0; // fcvt.lu.s s->lu + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase - 7'b1111000: ControlsD = `FCTRLW'b1_0_11_000_000_00_0_0; // fmv.w.x - 7'b010000?: ControlsD = `FCTRLW'b1_0_11_000_100_00_0_0; // fcvt.s.d + 7'b1111000: ControlsD = `FCTRLW'b1_0_11_000_00_00_0_0; // fmv.w.x + 7'b0100000: ControlsD = `FCTRLW'b1_0_11_000_11_00_0_0; // fcvt.s.d 7'b1101001: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b1_0_11_000_011_00_0_0; // fcvt.d.w - 2'b01: ControlsD = `FCTRLW'b1_0_11_010_011_00_0_0; // fcvt.d.wu - 2'b10: ControlsD = `FCTRLW'b1_0_11_100_011_00_0_0; // fcvt.d.l - 2'b11: ControlsD = `FCTRLW'b1_0_11_110_011_00_0_0; // fcvt.d.lu - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 2'b00: ControlsD = `FCTRLW'b1_0_11_101_11_00_0_0; // fcvt.d.w w->d + 2'b01: ControlsD = `FCTRLW'b1_0_11_100_11_00_0_0; // fcvt.d.wu wu->d + 2'b10: ControlsD = `FCTRLW'b1_0_11_111_11_00_0_0; // fcvt.d.l l->d + 2'b11: ControlsD = `FCTRLW'b1_0_11_110_11_00_0_0; // fcvt.d.lu lu->d + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase 7'b1100001: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b0_1_11_001_011_11_0_0; // fcvt.w.d - 2'b01: ControlsD = `FCTRLW'b0_1_11_011_011_11_0_0; // fcvt.wu.d - 2'b10: ControlsD = `FCTRLW'b0_1_11_101_011_11_0_0; // fcvt.l.d - 2'b11: ControlsD = `FCTRLW'b0_1_11_111_011_11_0_0; // fcvt.lu.d - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 2'b00: ControlsD = `FCTRLW'b0_1_11_001_11_11_0_0; // fcvt.w.d d->w + 2'b01: ControlsD = `FCTRLW'b0_1_11_000_11_11_0_0; // fcvt.wu.d d->wu + 2'b10: ControlsD = `FCTRLW'b0_1_11_011_11_11_0_0; // fcvt.l.d d->l + 2'b11: ControlsD = `FCTRLW'b0_1_11_010_11_11_0_0; // fcvt.lu.d d->lu + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase - 7'b1111001: ControlsD = `FCTRLW'b1_0_11_001_000_00_0_0; // fmv.d.x - //7'b0100001: ControlsD = `FCTRLW'b1_0_11_000_100_00_0_0; // fcvt.d.s - default: ControlsD = `FCTRLW'b0_0_00_000_100_00_0_1; // non-implemented instruction + 7'b1111001: ControlsD = `FCTRLW'b1_0_11_001_00_00_0_0; // fmv.d.x + 7'b0100001: ControlsD = `FCTRLW'b1_0_11_001_11_00_0_0; // fcvt.d.s + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + default: ControlsD = `FCTRLW'b0_0_00_000_00_00_0_1; // non-implemented instruction endcase // unswizzle control bits @@ -119,7 +119,7 @@ module fctrl ( // Precision // 0-single // 1-double - assign FmtD = FResultSelD == 2'b00 ? Funct3D[0] : FResSelD == 3'b100 | OpD[6:1] == 6'b010000 ? ~Funct7D[0] : Funct7D[0]; + assign FmtD = FResultSelD == 2'b00 ? Funct3D[0] : ((Funct7D[6:3] == 4'b0100)&OpD[4]) | OpD[6:1] == 6'b010000 ? ~Funct7D[0] : Funct7D[0]; // FResultSel: // 000 - ReadRes - load diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 431e6d6e0..97735c5f7 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -599,7 +599,7 @@ module normalize( /////////////////////////////////////////////////////////////////////////////// // Normalization /////////////////////////////////////////////////////////////////////////////// - + //*** insert bias-bias simplification in fcvt.sv/phone pictures/ whiteboard... if still there // Determine if the sum is zero assign SumZero = ~(|SumM); diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index b4b5a2e98..c876a26ae 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -72,7 +72,7 @@ module fpu ( logic [1:0] FResultSelD, FResultSelE; // Select the result written to FP register logic [1:0] FResultSelM, FResultSelW; // Select the result written to FP register logic [2:0] FOpCtrlD, FOpCtrlE; // Select which opperation to do in each component - logic [2:0] FResSelD, FResSelE; // Select one of the results that finish in the memory stage + logic [1:0] FResSelD, FResSelE; // Select one of the results that finish in the memory stage logic [1:0] FIntResSelD, FIntResSelE; // Select the result written to the integer resister logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input @@ -104,7 +104,7 @@ module fpu ( logic XInfQ, YInfQ; // is the input infinity - divide logic XExpMaxE; // is the exponent all ones (max value) logic XNormE; // is normal - logic ZOrigDenormE; + logic ZOrigDenormE, XOrigDenormE; logic FmtQ; logic FOpCtrlQ; @@ -114,9 +114,8 @@ module fpu ( logic [63:0] FMAResM, FMAResW; // FMA/multiply result logic [4:0] FMAFlgM; // FMA/multiply result logic [63:0] ReadResW; // read result (load instruction) - logic [63:0] CvtFpResE; // add/FP -> FP convert result - logic [4:0] CvtFpFlgE; // add/FP -> FP convert flags logic [63:0] CvtResE; // FP <-> int convert result + logic [`XLEN-1:0] CvtIntResE; // FP <-> int convert result logic [4:0] CvtFlgE; // FP <-> int convert flags //*** trim this logic [63:0] ClassResE; // classify result logic [63:0] CmpResE; // compare result @@ -152,7 +151,7 @@ module fpu ( flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E); flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, {Adr1E, Adr2E, Adr3E}); - flopenrc #(17) DECtrlReg3(clk, reset, FlushE, ~StallE, + flopenrc #(16) DECtrlReg3(clk, reset, FlushE, ~StallE, {FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD, FDivStartD}, {FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE, FDivStartE}); @@ -177,7 +176,7 @@ module fpu ( // unpack unit // - splits FP inputs into their various parts // - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity) - unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, .ZOrigDenormE, + unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, .ZOrigDenormE, .XOrigDenormE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); @@ -214,13 +213,12 @@ module fpu ( .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); // other FP execution units - fcvtfp fcvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE); fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE); fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE); fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE); - fcvtint fcvtint (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE, - .CvtResE, .CvtFlgE); + fcvt fcvt (.XSgnE, .XExpE, .XManE, .ForwardedSrcAE, .FOpCtrlE, .FWriteIntE, .XZeroE, .XOrigDenormE, + .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtResE, .CvtIntResE, .CvtFlgE); // data to be stored in memory - to IEU // - FP uses NaN-blocking format @@ -231,12 +229,12 @@ module fpu ( mux2 #(64) SrcAMux({{32{1'b1}}, ForwardedSrcAE[31:0]}, {{64-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // select a result that may be written to the FP register - mux5 #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, CvtFpResE, FResSelE, FResE); - mux5 #(5) FFlgMux(5'b0, 5'b0, {CmpNVE, 4'b0}, CvtFlgE, CvtFpFlgE, FResSelE, FFlgE); + mux4 #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, FResSelE, FResE); + mux4 #(5) FFlgMux(5'b0, 5'b0, {CmpNVE, 4'b0}, CvtFlgE, FResSelE, FFlgE); // select the result that may be written to the integer register - to IEU mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0], - CvtResE[`XLEN-1:0], FIntResSelE, FIntResE); + CvtIntResE, FIntResSelE, FIntResE); // E/M pipe registers diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index c45f86d2e..44ffc2838 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -12,7 +12,7 @@ module unpack ( output logic XDenormE, YDenormE, ZDenormE, // is XYZ denormalized output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero output logic XInfE, YInfE, ZInfE, // is XYZ infinity - output logic ZOrigDenormE, // is the original precision denormalized + output logic XOrigDenormE, ZOrigDenormE, // is the original precision denormalized output logic XExpMaxE // does X have the maximum exponent (NaN or Inf) ); @@ -49,6 +49,7 @@ module unpack ( assign YExpMaxE = &YExpE; assign ZExpMaxE = &ZExpE; + assign XOrigDenormE = 1'b0; assign ZOrigDenormE = 1'b0; @@ -73,7 +74,7 @@ module unpack ( // double and half logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed - logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized + logic YOrigDenormE; // the original value of XYZ is denormalized // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; @@ -141,7 +142,7 @@ module unpack ( logic [`LEN1-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for larger percision logic [`LEN2-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for smallest precision - logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized + logic YOrigDenormE; // the original value of XYZ is denormalized // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for larger precision assign XLen1 = &X[`FLEN-1:`LEN1] ? X[`LEN1-1:0] : {1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; @@ -318,7 +319,7 @@ module unpack ( logic [`D_LEN-1:0] XLen1, YLen1, ZLen1; // Remove NaN boxing or NaN, if not properly NaN boxed for double percision logic [`S_LEN-1:0] XLen2, YLen2, ZLen2; // Remove NaN boxing or NaN, if not properly NaN boxed for single percision logic [`H_LEN-1:0] XLen3, YLen3, ZLen3; // Remove NaN boxing or NaN, if not properly NaN boxed for half percision - logic XOrigDenormE, YOrigDenormE; // the original value of XYZ is denormalized + logic YOrigDenormE; // the original value of XYZ is denormalized // Check NaN boxing, If the value is not properly NaN boxed, set the value to a quiet NaN - for double precision assign XLen1 = &X[`Q_LEN-1:`D_LEN] ? X[`D_LEN-1:0] : {1'b0, {`D_NE+1{1'b1}}, (`D_NF-1)'(0)}; diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 9e8a35167..0870acad4 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -17,6 +17,7 @@ module testbenchfp; string FmaRnmTests[]; // list of FMA round to nearest max magnitude logic [2:0] OpCtrl[]; // list of op controls logic [2:0] Unit[]; // list of units being tested + logic WriteInt[]; // Is being written to integer resgiter logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100 logic [1:0] Fmt[]; // list of formats for the other units logic [1:0] FmaFmt[]; // list of formats for the FMA @@ -37,6 +38,7 @@ module testbenchfp; logic [1:0] FmaFmtVal, FmtVal; // value of the current Fmt logic [2:0] UnitVal, OpCtrlVal, FrmVal; // vlaue of the currnet Unit/OpCtrl/FrmVal + logic WriteIntVal; // value of the current WriteInt logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat logic [`FLEN-1:0] FmaRneX, FmaRneY, FmaRneZ; // inputs read from TestFloat logic [`FLEN-1:0] FmaRzX, FmaRzY, FmaRzZ; // inputs read from TestFloat @@ -53,8 +55,9 @@ module testbenchfp; logic [4:0] ResFlg; // Result flags logic [4:0] FmaRneResFlg, FmaRzResFlg, FmaRuResFlg, FmaRdResFlg, FmaRnmResFlg; // flags read form testfloat logic [`FPSIZES/3:0] ModFmt, FmaModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad - logic [`FLEN-1:0] FmaRes, DivRes, CmpRes, CvtRes, CvtFpRes; // Results from each unit - logic [4:0] FmaFlg, CvtFpFlg, DivFlg, CvtIntFlg, CmpFlg; // Outputed flags + logic [`FLEN-1:0] FmaRes, DivRes, CmpRes, CvtRes; // Results from each unit + logic [`XLEN-1:0] CvtIntRes; // Results from each unit + logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags logic ResNaN, FmaRneResNaN, FmaRzResNaN, FmaRuResNaN, FmaRdResNaN, FmaRnmResNaN; // is the outputed result NaN logic AnsNaN, FmaRneAnsNaN, FmaRzAnsNaN, FmaRuAnsNaN, FmaRdAnsNaN, FmaRnmAnsNaN; // is the correct answer NaN logic NaNGood, FmaRneNaNGood, FmaRzNaNGood, FmaRuNaNGood, FmaRdNaNGood, FmaRnmNaNGood; // is the NaN answer correct @@ -150,6 +153,7 @@ module testbenchfp; Tests = {Tests, f128rv32cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; @@ -159,6 +163,7 @@ module testbenchfp; Tests = {Tests, f128rv64cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; @@ -172,39 +177,55 @@ module testbenchfp; Tests = {Tests, f128f64cvt}; // add the op-ctrls (i.e. the format of the result) OpCtrl = {OpCtrl, 3'b01, 3'b11}; + WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) - for(int i = 0; i<10; i++) begin + for(int i = 0; i<5; i++) begin Unit = {Unit, `CVTFPUNIT}; Fmt = {Fmt, 2'b11}; end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end end if(`F_SUPPORTED) begin // if single precision is supported // add the 128 <-> 32 bit conversions to the to-be-tested list Tests = {Tests, f128f32cvt}; // add the op-ctrls (i.e. the format of the result) OpCtrl = {OpCtrl, 3'b00, 3'b11}; + WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) - for(int i = 0; i<10; i++) begin + for(int i = 0; i<5; i++) begin Unit = {Unit, `CVTFPUNIT}; Fmt = {Fmt, 2'b11}; end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end end if(`ZFH_SUPPORTED) begin // if half precision is supported // add the 128 <-> 16 bit conversions to the to-be-tested list Tests = {Tests, f128f16cvt}; // add the op-ctrls (i.e. the format of the result) OpCtrl = {OpCtrl, 3'b10, 3'b11}; + WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) - for(int i = 0; i<10; i++) begin + for(int i = 0; i<5; i++) begin Unit = {Unit, `CVTFPUNIT}; Fmt = {Fmt, 2'b11}; end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; + end end end if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested // add the compare tests/op-ctrls/unit/fmt Tests = {Tests, f128cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; for(int i = 0; i<15; i++) begin Unit = {Unit, `CMPUNIT}; Fmt = {Fmt, 2'b11}; @@ -214,6 +235,7 @@ module testbenchfp; // add the addition tests/op-ctrls/unit/fmt Tests = {Tests, f128add}; OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b11}; @@ -223,6 +245,7 @@ module testbenchfp; // add the subtraction tests/op-ctrls/unit/fmt Tests = {Tests, f128sub}; OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b11}; @@ -232,6 +255,7 @@ module testbenchfp; // add the multiply tests/op-ctrls/unit/fmt Tests = {Tests, f128mul}; OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b11}; @@ -241,6 +265,7 @@ module testbenchfp; // add the divide tests/op-ctrls/unit/fmt Tests = {Tests, f128div}; OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b11}; @@ -250,6 +275,7 @@ module testbenchfp; // add the square-root tests/op-ctrls/unit/fmt Tests = {Tests, f128sqrt}; OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b11}; @@ -264,9 +290,7 @@ module testbenchfp; FmaRdTests = {FmaRdTests, "f128_mulAdd_rd.tv"}; FmaRnmTests = {FmaRnmTests, "f128_mulAdd_rnm.tv"}; // add the format for the Fma - for(int i = 0; i<5; i++) begin - FmaFmt = {FmaFmt, 2'b11}; - end + FmaFmt = {FmaFmt, 2'b11}; end end if (`D_SUPPORTED) begin // if double precision is supported @@ -274,6 +298,7 @@ module testbenchfp; Tests = {Tests, f64rv32cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; @@ -281,9 +306,10 @@ module testbenchfp; end if (`XLEN == 64) begin // if 64-bit integers are being supported Tests = {Tests, f64rv64cvtint}; - // add the op-codes for these tests to the op-code list + // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; - // add what unit is used and the fmt to their lists (one for each test) + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b01}; @@ -296,28 +322,39 @@ module testbenchfp; Tests = {Tests, f64f32cvt}; // add the op-ctrls (i.e. the format of the result) OpCtrl = {OpCtrl, 3'b00, 3'b01}; + WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) - for(int i = 0; i<10; i++) begin + for(int i = 0; i<5; i++) begin Unit = {Unit, `CVTFPUNIT}; Fmt = {Fmt, 2'b01}; end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end end if(`ZFH_SUPPORTED) begin // if half precision is supported // add the 64 <-> 16 bit conversions to the to-be-tested list Tests = {Tests, f64f16cvt}; // add the op-ctrls (i.e. the format of the result) OpCtrl = {OpCtrl, 3'b10, 3'b01}; + WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) - for(int i = 0; i<10; i++) begin + for(int i = 0; i<5; i++) begin Unit = {Unit, `CVTFPUNIT}; Fmt = {Fmt, 2'b01}; end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; + end end end if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; for(int i = 0; i<15; i++) begin Unit = {Unit, `CMPUNIT}; Fmt = {Fmt, 2'b01}; @@ -327,6 +364,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64add}; OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b01}; @@ -336,6 +374,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64sub}; OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b01}; @@ -345,6 +384,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64mul}; OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b01}; @@ -354,6 +394,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64div}; OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b01}; @@ -363,6 +404,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64sqrt}; OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b01}; @@ -376,9 +418,7 @@ module testbenchfp; FmaRuTests = {FmaRuTests, "f64_mulAdd_ru.tv"}; FmaRdTests = {FmaRdTests, "f64_mulAdd_rd.tv"}; FmaRnmTests = {FmaRnmTests, "f64_mulAdd_rnm.tv"}; - for(int i = 0; i<5; i++) begin - FmaFmt = {FmaFmt, 2'b01}; - end + FmaFmt = {FmaFmt, 2'b01}; end end if (`F_SUPPORTED) begin // if single precision being supported @@ -386,6 +426,7 @@ module testbenchfp; Tests = {Tests, f32rv32cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; @@ -393,9 +434,10 @@ module testbenchfp; end if (`XLEN == 64) begin // if 64-bit integers are supported Tests = {Tests, f32rv64cvtint}; - // add the op-codes for these tests to the op-code list + // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; - // add what unit is used and the fmt to their lists (one for each test) + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b00}; @@ -408,17 +450,23 @@ module testbenchfp; Tests = {Tests, f32f16cvt}; // add the op-ctrls (i.e. the format of the result) OpCtrl = {OpCtrl, 3'b10, 3'b00}; + WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) - for(int i = 0; i<10; i++) begin + for(int i = 0; i<5; i++) begin Unit = {Unit, `CVTFPUNIT}; Fmt = {Fmt, 2'b00}; end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; + end end end if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; for(int i = 0; i<15; i++) begin Unit = {Unit, `CMPUNIT}; Fmt = {Fmt, 2'b00}; @@ -428,6 +476,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32add}; OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b00}; @@ -437,6 +486,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32sub}; OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b00}; @@ -446,6 +496,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32mul}; OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b00}; @@ -455,6 +506,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32div}; OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b00}; @@ -464,6 +516,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32sqrt}; OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b00}; @@ -473,13 +526,11 @@ module testbenchfp; // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel FmaRneTests = {FmaRneTests, "f32_mulAdd_rne.tv"}; - // FmaRzTests = {FmaRzTests, "f32_mulAdd_rz.tv"}; - // FmaRuTests = {FmaRuTests, "f32_mulAdd_ru.tv"}; - // FmaRdTests = {FmaRdTests, "f32_mulAdd_rd.tv"}; - // FmaRnmTests = {FmaRnmTests, "f32_mulAdd_rnm.tv"}; - // for(int i = 0; i<5; i++) begin - FmaFmt = {FmaFmt, 2'b00}; - // end + FmaRzTests = {FmaRzTests, "f32_mulAdd_rz.tv"}; + FmaRuTests = {FmaRuTests, "f32_mulAdd_ru.tv"}; + FmaRdTests = {FmaRdTests, "f32_mulAdd_rd.tv"}; + FmaRnmTests = {FmaRnmTests, "f32_mulAdd_rnm.tv"}; + FmaFmt = {FmaFmt, 2'b00}; end end if (`ZFH_SUPPORTED) begin // if half precision supported @@ -487,6 +538,7 @@ module testbenchfp; Tests = {Tests, f16rv32cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; @@ -496,6 +548,7 @@ module testbenchfp; Tests = {Tests, f16rv64cvtint, f16rv32cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; @@ -507,6 +560,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; for(int i = 0; i<15; i++) begin Unit = {Unit, `CMPUNIT}; Fmt = {Fmt, 2'b10}; @@ -516,6 +570,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16add}; OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b10}; @@ -525,6 +580,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16sub}; OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b10}; @@ -534,6 +590,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16mul}; OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b10}; @@ -543,6 +600,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16div}; OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b10}; @@ -552,6 +610,7 @@ module testbenchfp; // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16sqrt}; OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; for(int i = 0; i<5; i++) begin Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b10}; @@ -561,13 +620,11 @@ module testbenchfp; // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel FmaRneTests = {FmaRneTests, "f16_mulAdd_rne.tv"}; - // FmaRzTests = {FmaRzTests, "f16_mulAdd_rz.tv"}; - // FmaRuTests = {FmaRuTests, "f16_mulAdd_ru.tv"}; - // FmaRdTests = {FmaRdTests, "f16_mulAdd_rd.tv"}; - // FmaRnmTests = {FmaRnmTests, "f16_mulAdd_rnm.tv"}; - // for(int i = 0; i<5; i++) begin - FmaFmt = {FmaFmt, 2'b10}; - // end + FmaRzTests = {FmaRzTests, "f16_mulAdd_rz.tv"}; + FmaRuTests = {FmaRuTests, "f16_mulAdd_ru.tv"}; + FmaRdTests = {FmaRdTests, "f16_mulAdd_rd.tv"}; + FmaRnmTests = {FmaRnmTests, "f16_mulAdd_rnm.tv"}; + FmaFmt = {FmaFmt, 2'b10}; end end @@ -606,6 +663,7 @@ module testbenchfp; always_comb UnitVal = Unit[TestNum]; always_comb FmtVal = Fmt[TestNum]; always_comb OpCtrlVal = OpCtrl[OpCtrlNum]; + always_comb WriteIntVal = WriteInt[OpCtrlNum]; always_comb FrmVal = Frm[FrmNum]; assign Mult = OpCtrlVal === 3'b100; @@ -673,7 +731,7 @@ module testbenchfp; readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, .XSgnE(XSgn), .YSgnE(YSgn), .ZSgnE(ZSgn), .Unit (UnitVal), .XExpE(XExp), .YExpE(YExp), .ZExpE(ZExp), .TestNum, .OpCtrl(OpCtrlVal), - .XManE(XMan), .YManE(YMan), .ZManE(ZMan), .ZOrigDenormE(ZOrigDenorm), + .XManE(XMan), .YManE(YMan), .ZManE(ZMan), .ZOrigDenormE(ZOrigDenorm), .XOrigDenormE(XOrigDenorm), .XNaNE(XNaN), .YNaNE(YNaN), .ZNaNE(ZNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .ZSNaNE(ZSNaN), .XDenormE(XDenorm), .YDenormE(YDenorm), .ZDenormE(ZDenorm), @@ -809,7 +867,12 @@ module testbenchfp; .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FmtM(ModFmt), .FrmM(FrmVal), .FMAFlgM(FmaFlg), .FMAResM(FmaRes), .Mult); // fcvtfp fcvtfp (.XExpE(XExp), .XManE(XMan), .XSgnE(XSgn), .XZeroE(XZero), .XDenormE(XDenorm), .XInfE(XInf), - // .XNaNE(XNaN), .XSNaNE(XSNaN), .FrmE(Frmal), .FmtE(ModFmt), .CvtFpRes, .CvtFpFlgE); + // .XNaNE(XNaN), .XSNaNE(XSNaN), .FrmE(FrmVal), .FmtE(ModFmt), .CvtFpResE(CvtFpRes), .CvtFpFlgE(CvtFpFlg)); + +fcvt fcvt (.XSgnE(XSgn), .XExpE(XExp), .XManE(XMan), .ForwardedSrcAE(SrcA), .FWriteIntE(WriteIntVal), + .XZeroE(XZero), .XOrigDenormE(XOrigDenorm), .FOpCtrlE(OpCtrlVal), + .XInfE(XInf), .XNaNE(XNaN), .XSNaNE(XSNaN), .FrmE(FrmVal), .FmtE(ModFmt), + .CvtResE(CvtRes), .CvtIntResE(CvtIntRes), .CvtFlgE(CvtFlg)); fcmp fcmp (.FmtE(ModFmt), .FOpCtrlE(OpCtrlVal), .XSgnE(XSgn), .YSgnE(YSgn), .XExpE(XExp), .YExpE(YExp), .XManE(XMan), .YManE(YMan), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .XSNaNE(XSNaN), .YSNaNE(YSNaN), .FSrcXE(X), .FSrcYE(Y), .CmpNVE(CmpFlg[4]), .CmpResE(CmpRes)); @@ -901,38 +964,55 @@ module testbenchfp; AnsNaN = 1'b0; ResNaN = 1'b0; end - else begin - case (FmtVal) + else if (UnitVal === `CVTFPUNIT) begin + case (OpCtrlVal[1:0]) 4'b11: begin // quad - AnsNaN = &Ans[`FLEN-2:`NF]&(|Ans[`NF-1:0]); - ResNaN = &FmaRes[`FLEN-2:`NF]&(|FmaRes[`NF-1:0]); + AnsNaN = &Ans[`Q_LEN-2:`NF]&(|Ans[`Q_NF-1:0]); + ResNaN = &Res[`Q_LEN-2:`NF]&(|Res[`Q_NF-1:0]); end 4'b01: begin // double - AnsNaN = &Ans[`LEN1-2:`NF1]&(|Ans[`NF1-1:0]); - ResNaN = &FmaRes[`LEN1-2:`NF1]&(|FmaRes[`NF1-1:0]); + AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); + ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); end 4'b00: begin // single - AnsNaN = &Ans[`LEN2-2:`NF2]&(|Ans[`NF2-1:0]); - ResNaN = &FmaRes[`LEN2-2:`NF2]&(|FmaRes[`NF2-1:0]); + AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); + ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); end 4'b10: begin // half AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); - ResNaN = &FmaRes[`H_LEN-2:`H_NF]&(|FmaRes[`H_NF-1:0]); + ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); + end + endcase + end + else begin + case (FmtVal) + 4'b11: begin // quad + AnsNaN = &Ans[`Q_LEN-2:`Q_NF]&(|Ans[`Q_NF-1:0]); + ResNaN = &Res[`Q_LEN-2:`Q_NF]&(|Res[`Q_NF-1:0]); + end + 4'b01: begin // double + AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); + ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); + end + 4'b00: begin // single + AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); + ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); + end + 4'b10: begin // half + AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); + ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); end endcase end end - - // check results on falling edge of clk - always @(negedge clk) begin - +always_comb begin // select the result to check case (UnitVal) `FMAUNIT: Res = FmaRes; `DIVUNIT: Res = DivRes; `CMPUNIT: Res = CmpRes; - `CVTINTUNIT: Res = CvtRes; - `CVTFPUNIT: Res = CvtFpRes; + `CVTINTUNIT: if(WriteIntVal) Res = CvtIntRes; else Res = CvtRes; + `CVTFPUNIT: Res = CvtRes; endcase // select the flag to check @@ -940,9 +1020,13 @@ module testbenchfp; `FMAUNIT: ResFlg = FmaFlg; `DIVUNIT: ResFlg = DivFlg; `CMPUNIT: ResFlg = CmpFlg; - `CVTINTUNIT: ResFlg = CvtIntFlg; - `CVTFPUNIT: ResFlg = CvtFpFlg; + `CVTINTUNIT: ResFlg = CvtFlg; + `CVTFPUNIT: ResFlg = CvtFlg; endcase +end + // check results on falling edge of clk + always @(negedge clk) begin + // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: // - the sign of the NaN does not matter for the opperations being tested @@ -1060,15 +1144,19 @@ module testbenchfp; else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format case (OpCtrlVal[1:0]) 2'b11: NaNGood = ((AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) | (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); 2'b01: NaNGood = ((AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) | (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); 2'b00: NaNGood = ((AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) | (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); 2'b10: NaNGood = ((AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) | (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); endcase @@ -1086,15 +1174,23 @@ module testbenchfp; /////////////////////////////////////////////////////////////////////////////////////////////// // check if the non-fma test is correct - if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(UnitVal !== `CMPUNIT)) begin + if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(UnitVal !== `CVTINTUNIT)) begin errors += 1; $display("There is an error in %s", Tests[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; end - // in The RISC-V Instruction Set Manual (2019) section 11.8 specifies that - // if a any of the inputs to the EQ LT LE opperations then the opperation should return a 0 - else if ((UnitVal === `CMPUNIT)&(XNaN|YNaN)&(Res !== (`FLEN)'(0))) begin + + // TestFloat sets the result to all 1's when there is an invalid result, however in + // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says + // for an unsigned integer result 0 is also okay + + // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but + // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... + else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&XSgn&(Res === (`FLEN)'(0))) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&OpCtrlVal[1]&(Res === {1'b0, {`FLEN-1{1'b1}}})) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&~OpCtrlVal[1]&(Res === {{`FLEN{1'b0}}, 1'b0, {31{1'b1}}})) | + (Res === Ans | NaNGood | NaNGood === 1'bx)) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin errors += 1; $display("There is an error in %s", Tests[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); @@ -1147,6 +1243,8 @@ module testbenchfp; // increment the test TestNum += 1; + // clear the vectors + for(int i=0; i<46465; i++) TestVectors[i] = {`FLEN*4+8{1'bx}}; // read next files $readmemh({`PATH, Tests[TestNum]}, TestVectors); $readmemh({`PATH, FmaRneTests[TestNum]}, FmaRneVectors); @@ -1211,6 +1309,7 @@ module readfmavectors ( ); logic XNormE, XExpMaxE; // signals the unpacker outputs but isn't used in FMA + logic XOrigDenormE; // apply test vectors on rising edge of clk // Format of vectors Inputs(1/2/3)_AnsFlg always @(posedge clk) begin @@ -1244,7 +1343,7 @@ module readfmavectors ( endcase end - unpack unpack(.X, .Y, .Z, .FmtE(FmaModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, + unpack unpack(.X, .Y, .Z, .FmtE(FmaModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XOrigDenormE, .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .ZOrigDenormE); @@ -1287,7 +1386,7 @@ module readvectors ( output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero output logic XInfE, YInfE, ZInfE, // is XYZ infinity output logic XNormE, XExpMaxE, - output logic ZOrigDenormE, + output logic ZOrigDenormE, XOrigDenormE, output logic [`FLEN-1:0] X, Y, Z ); @@ -1464,89 +1563,105 @@ module readvectors ( case (Fmt) 2'b11: begin // quad // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2], OpCtrl[0]}) + casex ({OpCtrl[2:1]}) 2'b11: begin // long -> quad + X = {`FLEN{1'bx}}; SrcA = TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]; Ans = TestVector[8+(`Q_LEN-1):8]; end - 2'b01: begin // int -> quad + 2'b10: begin // int -> quad // correctly sign extend the integer depending on if it's a signed/unsigned test - SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]}; + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+32-1]}}, TestVector[8+`Q_LEN+32-1:8+(`Q_LEN)]}; Ans = TestVector[8+(`Q_LEN-1):8]; end - 2'b10: begin // quad -> long + 2'b01: begin // quad -> long X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; Ans = {TestVector[8+(`XLEN-1):8]}; end - 2'b00: begin // double -> long - X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; - Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}},TestVector[8+(`XLEN-1):8]}; + 2'b00: begin // quad -> int + X = {{`FLEN-`Q_LEN{1'b1}}, TestVector[8+32+`Q_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end 2'b01: begin // double - // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2], OpCtrl[0]}) + // {Int->Fp?, is the integer a long} + casex ({OpCtrl[2:1]}) 2'b11: begin // long -> double + X = {`FLEN{1'bx}}; SrcA = TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]; - Ans = TestVector[8+(`D_LEN-1):8]; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; end - 2'b01: begin // int -> double + 2'b10: begin // int -> double // correctly sign extend the integer depending on if it's a signed/unsigned test - SrcA = {{`XLEN-32{TestVector[8+`D_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]}; - Ans = TestVector[8+(`D_LEN-1):8]; + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`D_LEN+32-1]}}, TestVector[8+`D_LEN+32-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; end - 2'b10: begin // double -> long + 2'b01: begin // double -> long X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; Ans = {TestVector[8+(`XLEN-1):8]}; end 2'b00: begin // double -> int - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; - Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}},TestVector[8+(`XLEN-1):8]}; + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+32+`D_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end 2'b00: begin // single // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2], OpCtrl[0]}) + casex ({OpCtrl[2:1]}) 2'b11: begin // long -> single + X = {`FLEN{1'bx}}; SrcA = TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]; - Ans = TestVector[8+(`S_LEN-1):8]; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; end - 2'b01: begin // int -> single + 2'b10: begin // int -> single // correctly sign extend the integer depending on if it's a signed/unsigned test - SrcA = {{`XLEN-32{TestVector[8+`S_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]}; - Ans = TestVector[8+(`S_LEN-1):8]; + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`S_LEN+32-1]}}, TestVector[8+`S_LEN+32-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; end - 2'b10: begin // single -> long + 2'b01: begin // single -> long X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; Ans = {TestVector[8+(`XLEN-1):8]}; end 2'b00: begin // single -> int - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; - Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}},TestVector[8+(`XLEN-1):8]}; + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+32+`S_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end 2'b10: begin // half // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2], OpCtrl[0]}) + casex ({OpCtrl[2:1]}) 2'b11: begin // long -> half + X = {`FLEN{1'bx}}; SrcA = TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]; - Ans = TestVector[8+(`H_LEN-1):8]; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; end - 2'b01: begin // int -> half + 2'b10: begin // int -> half // correctly sign extend the integer depending on if it's a signed/unsigned test - SrcA = {{`XLEN-32{TestVector[8+`H_LEN+`XLEN]&~OpCtrl[1]}}, TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]}; - Ans = TestVector[8+(`H_LEN-1):8]; + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`H_LEN+32-1]}}, TestVector[8+`H_LEN+32-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; end - 2'b10: begin // half -> long + 2'b01: begin // half -> long X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; Ans = {TestVector[8+(`XLEN-1):8]}; end 2'b00: begin // half -> int - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; - Ans = {{`XLEN-32{TestVector[8+`XLEN]&~OpCtrl[1]}}, TestVector[8+(`XLEN-1):8]}; + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+32+`H_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; end endcase end @@ -1557,5 +1672,5 @@ module readvectors ( unpack unpack(.X, .Y, .Z, .FmtE(ModFmt), .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, - .XExpMaxE, .ZOrigDenormE); + .XExpMaxE, .ZOrigDenormE, .XOrigDenormE); endmodule \ No newline at end of file diff --git a/pipelined/testbench/tests-fp.vh b/pipelined/testbench/tests-fp.vh index d285454bb..d872da717 100644 --- a/pipelined/testbench/tests-fp.vh +++ b/pipelined/testbench/tests-fp.vh @@ -34,14 +34,14 @@ `define LE_OPCTRL 3'b011 `define LT_OPCTRL 3'b001 `define EQ_OPCTRL 3'b010 -`define TO_UI_OPCTRL 3'b011 +`define TO_UI_OPCTRL 3'b000 `define TO_I_OPCTRL 3'b001 -`define TO_UL_OPCTRL 3'b111 -`define TO_L_OPCTRL 3'b101 -`define FROM_UI_OPCTRL 3'b010 -`define FROM_I_OPCTRL 3'b000 +`define TO_UL_OPCTRL 3'b010 +`define TO_L_OPCTRL 3'b011 +`define FROM_UI_OPCTRL 3'b100 +`define FROM_I_OPCTRL 3'b101 `define FROM_UL_OPCTRL 3'b110 -`define FROM_L_OPCTRL 3'b100 +`define FROM_L_OPCTRL 3'b111 `define RNE 3'b000 `define RZ 3'b001 `define RU 3'b011 diff --git a/tests/fp/create_vectors.sh b/tests/fp/create_vectors.sh index bac71c608..3dfad885d 100755 --- a/tests/fp/create_vectors.sh +++ b/tests/fp/create_vectors.sh @@ -98,101 +98,101 @@ $BUILD/testfloat_gen -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv $BUILD/testfloat_gen -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv $BUILD/testfloat_gen -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv echo "Creating f16_to_ui32 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv -$BUILD/testfloat_gen -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv -$BUILD/testfloat_gen -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv +$BUILD/testfloat_gen -rminMag -exact f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv +$BUILD/testfloat_gen -rmax -exact f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv +$BUILD/testfloat_gen -rmin -exact f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv echo "Creating f32_to_ui32 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv -$BUILD/testfloat_gen -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv -$BUILD/testfloat_gen -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv +$BUILD/testfloat_gen -rminMag -exact f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv +$BUILD/testfloat_gen -rmax -exact f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv +$BUILD/testfloat_gen -rmin -exact f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv echo "Creating f64_to_ui32 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv -$BUILD/testfloat_gen -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv -$BUILD/testfloat_gen -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv +$BUILD/testfloat_gen -rminMag -exact f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv +$BUILD/testfloat_gen -rmax -exact f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv +$BUILD/testfloat_gen -rmin -exact f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv echo "Creating f128_to_ui32 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv -$BUILD/testfloat_gen -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv -$BUILD/testfloat_gen -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv +$BUILD/testfloat_gen -rminMag -exact f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv +$BUILD/testfloat_gen -rmax -exact f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv +$BUILD/testfloat_gen -rmin -exact f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv echo "Creating f16_to_ui64 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv -$BUILD/testfloat_gen -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv -$BUILD/testfloat_gen -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv +$BUILD/testfloat_gen -rminMag -exact f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv +$BUILD/testfloat_gen -rmax -exact f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv +$BUILD/testfloat_gen -rmin -exact f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv echo "Creating f32_to_ui64 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv -$BUILD/testfloat_gen -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv -$BUILD/testfloat_gen -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv +$BUILD/testfloat_gen -rminMag -exact f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv +$BUILD/testfloat_gen -rmax -exact f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv +$BUILD/testfloat_gen -rmin -exact f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv echo "Creating f64_to_ui64 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv -$BUILD/testfloat_gen -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv -$BUILD/testfloat_gen -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv +$BUILD/testfloat_gen -rminMag -exact f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv +$BUILD/testfloat_gen -rmax -exact f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv +$BUILD/testfloat_gen -rmin -exact f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv echo "Creating f128_to_ui64 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv -$BUILD/testfloat_gen -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv -$BUILD/testfloat_gen -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv +$BUILD/testfloat_gen -rminMag -exact f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv +$BUILD/testfloat_gen -rmax -exact f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv +$BUILD/testfloat_gen -rmin -exact f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv echo "Creating f16_to_i32 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv -$BUILD/testfloat_gen -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv -$BUILD/testfloat_gen -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv +$BUILD/testfloat_gen -rminMag -exact f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv +$BUILD/testfloat_gen -rmax -exact f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv +$BUILD/testfloat_gen -rmin -exact f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv echo "Creating f32_to_i32 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv -$BUILD/testfloat_gen -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv -$BUILD/testfloat_gen -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv +$BUILD/testfloat_gen -rminMag -exact f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv +$BUILD/testfloat_gen -rmax -exact f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv +$BUILD/testfloat_gen -rmin -exact f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv echo "Creating f64_to_i32 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv -$BUILD/testfloat_gen -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv -$BUILD/testfloat_gen -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv +$BUILD/testfloat_gen -rminMag -exact f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv +$BUILD/testfloat_gen -rmax -exact f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv +$BUILD/testfloat_gen -rmin -exact f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv echo "Creating f128_to_i32 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv -$BUILD/testfloat_gen -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv -$BUILD/testfloat_gen -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv +$BUILD/testfloat_gen -rminMag -exact f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv +$BUILD/testfloat_gen -rmax -exact f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv +$BUILD/testfloat_gen -rmin -exact f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv echo "Creating f16_to_i64 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv -$BUILD/testfloat_gen -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv -$BUILD/testfloat_gen -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv +$BUILD/testfloat_gen -rminMag -exact f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv +$BUILD/testfloat_gen -rmax -exact f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv +$BUILD/testfloat_gen -rmin -exact f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv echo "Creating f32_to_i64 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv -$BUILD/testfloat_gen -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv -$BUILD/testfloat_gen -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv +$BUILD/testfloat_gen -rminMag -exact f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv +$BUILD/testfloat_gen -rmax -exact f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv +$BUILD/testfloat_gen -rmin -exact f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv echo "Creating f64_to_i64 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv -$BUILD/testfloat_gen -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv -$BUILD/testfloat_gen -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv +$BUILD/testfloat_gen -rminMag -exact f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv +$BUILD/testfloat_gen -rmax -exact f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv +$BUILD/testfloat_gen -rmin -exact f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv echo "Creating f128_to_i64 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv -$BUILD/testfloat_gen -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv -$BUILD/testfloat_gen -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv +$BUILD/testfloat_gen -rnear_even -exact f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv +$BUILD/testfloat_gen -rminMag -exact f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv +$BUILD/testfloat_gen -rmax -exact f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv +$BUILD/testfloat_gen -rmin -exact f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv +$BUILD/testfloat_gen -rnear_maxMag -exact f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv echo "Creating f16_to_f32 convert vectors" $BUILD/testfloat_gen -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv $BUILD/testfloat_gen -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv From 650779318d498071bf9625e8e6ba281737940a35 Mon Sep 17 00:00:00 2001 From: cturek Date: Wed, 25 May 2022 23:36:21 +0000 Subject: [PATCH 07/28] Fixed exponent verification, added sign module and added sign tests --- addins/riscv-arch-test | 2 +- pipelined/srt/exptestgen.c | 19 +- pipelined/srt/srt.sv | 33 ++- pipelined/srt/testbench.sv | 40 ++-- pipelined/srt/testvectors | 418 ++++++++++++++++++------------------- 5 files changed, 272 insertions(+), 240 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99bd..307c77b26 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 diff --git a/pipelined/srt/exptestgen.c b/pipelined/srt/exptestgen.c index 2d5cfb861..09166c1ff 100644 --- a/pipelined/srt/exptestgen.c +++ b/pipelined/srt/exptestgen.c @@ -21,7 +21,7 @@ /* Prototypes */ -void output(FILE *fptr, int e1, double a, int e2, double b, int r_exp, double r_mantissa); +void output(FILE *fptr, int signa, int e1, double a, int signb, int e2, double b, int r_sign, int r_exp, double r_mantissa); void printhex(FILE *fptr, double x); double random_input(void); double random_input_e(void); @@ -35,8 +35,8 @@ void main(void) // a & b are mantissas // r_mantissa is result of mantissa divsion // r_exp is result of exponent division - double a, b, r_mantissa, r_exp; - int e1, e2; + double a, b, r_mantissa, r_exp, r_sign; + int e1, e2, signa, signb; double mantissa[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -53,12 +53,15 @@ void main(void) for (i=0; i 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp + if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp begin errors = errors+1; $display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp); $display("failed\n"); $stop; end - if (a === 52'hxxxxxxxxxxxxx) + if (afrac === 52'hxxxxxxxxxxxxx) begin $display("%d Tests completed successfully", testnum); $stop; @@ -124,9 +130,11 @@ module testbench; testnum = testnum+1; Vec = Tests[testnum]; $display("a = %h b = %h",a,b); - a = Vec[`mema]; - b = Vec[`memb]; - nextr = Vec[`memr]; + a = Vec[`mema]; + {asign, aExp, afrac} = a; + b = Vec[`memb]; + {bsign, bExp, bfrac} = b; + nextr = Vec[`memr]; end end diff --git a/pipelined/srt/testvectors b/pipelined/srt/testvectors index c6412a9e6..de0b5f5cc 100644 --- a/pipelined/srt/testvectors +++ b/pipelined/srt/testvectors @@ -1,289 +1,289 @@ 4000000000000000_4000000000000000_3ff0000000000000 -4018000000000000_4000000000000000_4008000000000000 +c018000000000000_4000000000000000_c008000000000000 4024000000000000_4000000000000000_4014000000000000 -4032000000000000_4000000000000000_4022000000000000 +c032000000000000_4000000000000000_c022000000000000 4041000000000000_4000000000000000_4031000000000000 -405c000000000000_4000000000000000_404c000000000000 +c05c000000000000_4000000000000000_c04c000000000000 406e000000000000_4000000000000000_405e000000000000 -407ffff583a53b8e_4000000000000000_406ffff583a53b8e +c07ffff583a53b8e_4000000000000000_c06ffff583a53b8e 408199999999999a_4000000000000000_407199999999999a -4093333333333333_4000000000000000_4083333333333333 +c093333333333333_4000000000000000_c083333333333333 40a028f5c28f5c29_4000000000000000_409028f5c28f5c29 -40b004189374bc6a_4000000000000000_40a004189374bc6a +c0b004189374bc6a_4000000000000000_c0a004189374bc6a 40c00068db8bac71_4000000000000000_40b00068db8bac71 -40dd1745d1745d17_4000000000000000_40cd1745d1745d17 +c0dd1745d1745d17_4000000000000000_c0cd1745d1745d17 40e5555555555555_4000000000000000_40d5555555555555 -40f999999999999a_4000000000000000_40e999999999999a +c0f999999999999a_4000000000000000_c0e999999999999a 410c71c71c71c71c_4000000000000000_40fc71c71c71c71c -4000000000000000_4018000000000000_3fe5555555555555 -4018000000000000_4018000000000000_3ff0000000000000 -4024000000000000_4018000000000000_400aaaaaaaaaaaab -4032000000000000_4018000000000000_4018000000000000 -4041000000000000_4018000000000000_4026aaaaaaaaaaab -405c000000000000_4018000000000000_4032aaaaaaaaaaab -406e000000000000_4018000000000000_4044000000000000 -407ffff583a53b8e_4018000000000000_4055554e57c37d09 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+40a028f5c28f5c29_c018000000000000_c0858bf258bf258c +c0b004189374bc6a_c018000000000000_40955acb6f46508d +40c00068db8bac71_c018000000000000_c0a555e124ba3b41 +c0dd1745d1745d17_c018000000000000_40b364d9364d9365 +40e5555555555555_c018000000000000_c0cc71c71c71c71c +c0f999999999999a_c018000000000000_40d1111111111111 +410c71c71c71c71c_c018000000000000_c0e2f684bda12f68 4000000000000000_4024000000000000_3fd999999999999a -4018000000000000_4024000000000000_3fe3333333333333 +c018000000000000_4024000000000000_bfe3333333333333 4024000000000000_4024000000000000_3ff0000000000000 -4032000000000000_4024000000000000_400ccccccccccccd +c032000000000000_4024000000000000_c00ccccccccccccd 4041000000000000_4024000000000000_401b333333333333 -405c000000000000_4024000000000000_4026666666666666 +c05c000000000000_4024000000000000_c026666666666666 406e000000000000_4024000000000000_4038000000000000 -407ffff583a53b8e_4024000000000000_40499991361dc93e +c07ffff583a53b8e_4024000000000000_c0499991361dc93e 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+c0b004189374bc6a_410c71c71c71c71c_bfa2049ba5e353f8 40c00068db8bac71_410c71c71c71c71c_3fb20075f6fd21ff -40dd1745d1745d17_410c71c71c71c71c_3fc05d1745d1745d +c0dd1745d1745d17_410c71c71c71c71c_bfc05d1745d1745d 40e5555555555555_410c71c71c71c71c_3fd8000000000000 -40f999999999999a_410c71c71c71c71c_3fecccccccccccce -410c71c71c71c71c_410c71c71c71c71c_3ff0000000000000 +c0f999999999999a_410c71c71c71c71c_bfecccccccccccce +410c71c71c71c71c_410c71c71c71c71c_3ff0000000000000 \ No newline at end of file From 366cd5f1d56c76defc6b359f63c836f6e19a8083 Mon Sep 17 00:00:00 2001 From: cturek Date: Thu, 26 May 2022 00:01:51 +0000 Subject: [PATCH 08/28] Renamed variables for readability --- pipelined/srt/exptestgen.c | 71 ++++++++++++++++++++------------------ pipelined/srt/testvectors | 2 +- 2 files changed, 38 insertions(+), 35 deletions(-) diff --git a/pipelined/srt/exptestgen.c b/pipelined/srt/exptestgen.c index 09166c1ff..bd51126e7 100644 --- a/pipelined/srt/exptestgen.c +++ b/pipelined/srt/exptestgen.c @@ -21,7 +21,7 @@ /* Prototypes */ -void output(FILE *fptr, int signa, int e1, double a, int signb, int e2, double b, int r_sign, int r_exp, double r_mantissa); +void output(FILE *fptr, int aSign, int aExp, double aFrac, int bSign, int bExp, double bFrac, int rSign, int rExp, double rFrac); void printhex(FILE *fptr, double x); double random_input(void); double random_input_e(void); @@ -31,12 +31,13 @@ double random_input_e(void); void main(void) { FILE *fptr; - // e1 & e2 are exponents - // a & b are mantissas - // r_mantissa is result of mantissa divsion - // r_exp is result of exponent division - double a, b, r_mantissa, r_exp, r_sign; - int e1, e2, signa, signb; + // aExp & bExp are exponents + // aFrac & bFrac are mantissas + // rFrac is result of fractional divsion + // rExp is result of exponent division + double aFrac, bFrac, rFrac; + int aExp, bExp, rExp; + int aSign, bSign, rSign; double mantissa[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -51,28 +52,28 @@ void main(void) } for (i=0; i Date: Wed, 25 May 2022 17:03:15 -0700 Subject: [PATCH 09/28] added logic to prevent cache line length from exceeding the max size of a burst. --- pipelined/testbench/testbench.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 4ebd37785..b40fcf365 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -373,6 +373,7 @@ module riscvassertions; assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); + assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16"); end endmodule From 5e875067721ffd3a7c4256ad4274f4662212b4d4 Mon Sep 17 00:00:00 2001 From: DTowersM Date: Thu, 26 May 2022 00:08:18 +0000 Subject: [PATCH 10/28] working makefile for embench and removed testbench-f64 --- benchmarks/embench/Makefile | 40 +++++++-- benchmarks/embench/Makefile~ | 7 -- pipelined/testbench/testbench-f64.sv | 123 --------------------------- 3 files changed, 31 insertions(+), 139 deletions(-) delete mode 100644 benchmarks/embench/Makefile~ delete mode 100755 pipelined/testbench/testbench-f64.sv diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index e26ed416d..3e40a68ab 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -1,15 +1,37 @@ # Makefile added 1/20/22 David_Harris@hmc.edu # Compile Embench for Wally -all: Makefile - ../../addins/embench-iot/build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cflags "-O2 -march=rv32i -mabi=ilp32 -mcmodel=medany" --cc riscv64-unknown-elf-gcc - ./benchmark_size.py - ./benchmark_speed.py +all: build sim -# view with -# more `ls -t | head -1` +allClean: clean all +build: + ../../addins/embench-iot/build_all.py --builddir=bd_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-nostartfiles" + ../../addins/embench-iot/build_all.py --builddir=bd_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib" --cflags="-nostdlib" --dummy-libs="libgcc libm libc crt0" + +sim: size speed + +size: + ../../addins/embench-iot/benchmark_size.py --builddir=bd_size + +speed: + ../../addins/embench-iot/benchmark_speed.py --builddir=bd_speed --target-module run_wally --cpu-mhz=50 + +objdump: + riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/aha-mont64/aha-mont64 > ../../addins/embench-iot/bd_speed/src/aha-mont64/aha-mont64.objdump + riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/cubic/cubic > ../../addins/embench-iot/bd_speed/src/cubic/cubic.objdump + riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/md5sum/md5sum > ../../addins/embench-iot/bd_speed/src/md5sum/md5sum.objdump + riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/statemate/statemate > ../../addins/embench-iot/bd_speed/src/statemate/statemate.objdump + +clean: + rm -rf ../../addins/embench-iot/bd_speed/ + rm -rf ../../addins/embench-iot/bd_size/ + +# std: +# ../../addins/embench-iot/build_all.py --builddir=bd_std --arch riscv32 --chip generic --board rv32wallyverilog --cc riscv64-unknown-elf-gcc --cflags="-v -c -O2 -ffunction-sections -march=rv32imac -mabi=ilp32" --ldflags="-Wl,-gc-sections -v -march=rv32imac -mabi=ilp32 ../../../../../benchmarks/embench/tohost.S -T../../../config/riscv32/boards/rv32wallyverilog/link.ld" --user-libs="-lm" +# riscv64-unknown-elf-objdump -D ../../addins/embench-iot/bd_std/src/aha-mont64/aha-mont64 > ../../addins/embench-iot/bd_std/src/aha-mont64/aha-mont64.objdump +# --dummy-libs="libgcc libm libc" # --cflags "-O2 -g -nostartfiles" - - -#riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c +# ../../addins/embench-iot/build_all.py --arch riscv32 --chip generic --board rv32wallyverilog --cc riscv64-unknown-elf-gcc --cflags="-c -Os -ffunction-sections -nostdlib -march=rv32imac -mabi=ilp32" --ldflags="-Wl,-gc-sections -nostdlib -march=rv32imac -mabi=ilp32 -T../../../config/riscv32/boards/rv32wallyverilog/link.ld" --dummy-libs="libgcc libm libc" +# --user-libs="-lm" +# riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c diff --git a/benchmarks/embench/Makefile~ b/benchmarks/embench/Makefile~ deleted file mode 100644 index ebd9a7e44..000000000 --- a/benchmarks/embench/Makefile~ +++ /dev/null @@ -1,7 +0,0 @@ -# Makefile added 1/20/22 David_Harris@hmc.edu -# Compile Embench for Wally - -all: Makefile - ./build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cc riscv64-unknown-elf-gcc - ./benchmark_size.py - ./benchmark_speed.py diff --git a/pipelined/testbench/testbench-f64.sv b/pipelined/testbench/testbench-f64.sv deleted file mode 100755 index a0c7e6a31..000000000 --- a/pipelined/testbench/testbench-f64.sv +++ /dev/null @@ -1,123 +0,0 @@ -// testbench -module testbench (); - - logic [63:0] op1; - logic [63:0] op2; - logic [2:0] FOpCtrlE; - logic [2:0] FrmE; - logic op_type; - logic FmtE; - logic OvEn; - logic UnEn; - - logic XSgnE, YSgnE, ZSgnE; - logic XSgnM, YSgnM; - logic [10:0] XExpE, YExpE, ZExpE; - logic [10:0] XExpM, YExpM, ZExpM; - logic [52:0] XManE, YManE, ZManE; - logic [52:0] XManM, YManM, ZManM; - - logic [10:0] BiasE; - logic XNaNE, YNaNE, ZNaNE; - logic XNaNM, YNaNM, ZNaNM; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XSNaNM, YSNaNM, ZSNaNM; - logic XDenormE, YDenormE, ZDenormE; - logic XZeroE, YZeroE, ZZeroE; - logic XZeroM, YZeroM, ZZeroM; - logic XInfE, YInfE, ZInfE; - logic XInfM, YInfM, ZInfM; - logic XExpMaxE; - logic XNormE; - logic FDivBusyE; - - logic start; - logic reset; - - logic XDenorm; - logic YDenorm; - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - unpack unpack(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE, - .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, - .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, - .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); - fpdiv fdivsqrt (.op1, .op2, .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]), - .reset, .clk, .start, .P(~FmtE), .OvEn(1'b0), .UnEn(1'b0), - .XNaNQ(XNaNE), .YNaNQ(YNaNE), .XInfQ(XInfE), .YInfQ(YInfE), .XZeroQ(XZeroE), .YZeroQ(YZeroE), - .FDivBusyE, .done(done), .AS_Result(AS_Result), .Flags(Flags)); - - - // current fpdivsqrt does not operation on denorms yet - assign Denorm = XDenormE | YDenormE | Flags[3]; - - // generate clock to sequence tests - always - begin - clk = 1; # 5; clk = 0; # 5; - end - - initial - begin - handle3 = $fopen("f64_div_rne.out"); - $readmemh("../testbench/fp/vectors/f64_div_rne.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - // Operation (if applicable) - #0 op_type = 1'b0; - // Precision (32-bit or 64-bit) - #0 FmtE = 1'b1; - // From fctrl logic to dictate operation - #0 FOpCtrlE = 3'b000; - // Rounding Mode - #0 FrmE = 3'b000; - // Trap masking (n/a for RISC-V) - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - if (testvectors[vectornum] === 200'bx) begin - $display("%d tests completed", vectornum); - $finish; - end - end // if (~reset) - $display("%d vectors processed", vectornum); - end // always @ (posedge clk) - -endmodule // tb - - From f4b9ade94274dd1ab4252fd6d510f34ad64b6f06 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 26 May 2022 00:10:51 +0000 Subject: [PATCH 11/28] added fcvt.sv --- addins/riscv-arch-test | 2 +- pipelined/src/fpu/fcvt.sv | 373 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 374 insertions(+), 1 deletion(-) create mode 100644 pipelined/src/fpu/fcvt.sv diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..be67c99bd 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv new file mode 100644 index 000000000..9195bc893 --- /dev/null +++ b/pipelined/src/fpu/fcvt.sv @@ -0,0 +1,373 @@ + +`include "wally-config.vh" +// largest length in IEU/FPU +`define LGLEN ((`NF<`XLEN) ? `XLEN : `NF) + +module fcvt ( + input logic XSgnE, // input's sign + input logic [`NE-1:0] XExpE, // input's exponent + input logic [`NF:0] XManE, // input's fraction + input logic [`XLEN-1:0] ForwardedSrcAE, // integer input - from IEU + input logic [2:0] FOpCtrlE, // choose which opperation (look below for values) + input logic FWriteIntE, // is fp->int (since it's writting to the integer register) + input logic XZeroE, // is the input zero + input logic XOrigDenormE, // is the input denormalized + input logic XInfE, // is the input infinity + input logic XNaNE, // is the input a NaN + input logic XSNaNE, // is the input a signaling NaN + input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude + input logic [`FPSIZES/3:0] FmtE, // the input's precision (11=quad 01=double 00=single 10=half) + output logic [`FLEN-1:0] CvtResE, // the fp to fp conversion's result + output logic [`XLEN-1:0] CvtIntResE, // the fp to fp conversion's result + output logic [4:0] CvtFlgE // the fp to fp conversion's flags + ); + + // OpCtrls: + // fp->fp conversions: {0, output precision} - only one of the operations writes to the int register + // half - 10 + // single - 00 + // double - 01 + // quad - 11 + // int<->fp conversions: {is int->fp?, is the integer 64-bit?, is the integer signed?} + // bit 2 bit 1 bit 0 + // for example: signed long -> single floating point has the OpCode 101 + + // (FF) fp -> fp coversion signals + // (IF) int -> fp coversion signals + // (FI) fp -> int coversion signals + + + logic [`FPSIZES/3:0] OutFmt; // format of the output + logic [`XLEN-1:0] PosInt; // the positive integer input + logic [`LGLEN-1:0] LzcIn; // input to the Leading Zero Counter (priority encoder) + logic [`NE:0] CalcExp; // the calculated expoent + logic [$clog2(`LGLEN):0] ShiftAmt; // how much to shift by + logic [`LGLEN+`NF:0] ShiftIn; // number to be shifted + logic ResDenormUf;// does the result underflow or is denormalized + logic ResUf; // does the result underflow + logic [`LGLEN+`NF:0] Shifted; // the shifted result + logic [`NE-2:0] NewBias; // the bias of the final result + logic [$clog2(`NF):0] ResNegNF; // the result's fraction length negated (-NF) + logic [`NE-1:0] OldExp; // the old exponent + logic ResSgn; // the result's sign + logic Sticky; // sticky bit - for rounding + logic Round; // round bit - for rounding + logic LSBFrac; // the least significant bit of the fraction - for rounding + logic CalcPlus1; // the calculated plus 1 + logic Plus1; // add one to the final result? + logic [`FLEN-1:0] ShiftedPlus1; // plus one shifted to the proper position + logic [`NE:0] FullResExp; // the full result exponent (with the overflow bit) + logic [`NE-1:0] ResExp; // the result's exponent (trimmed to the correct size) + logic [`NF-1:0] ResFrac; // the result's fraction + logic [`XLEN+1:0] NegRes; // the negation of the result + logic [`XLEN-1:0] OfIntRes; // the overflow result for integer output + logic Overflow, Underflow, Inexact, Invalid; // flags + logic IntInexact, FpInexact, IntInvalid, FpInvalid; // flags for FP and int outputs + logic [`NE-1:0] MaxExp; // the maximum exponent before overflow + logic [1:0] NegResMSBS; // the negitive integer result's most significant bits + logic [`FLEN-1:0] NaNRes, InfRes, Res, UfRes; //various special results + logic KillRes; // kill the result? + logic Signed; // is the opperation with a signed integer? + logic Int64; // is the integer 64 bits? + logic IntToFp; // is the opperation an int->fp conversion? + logic ToInt; // is the opperation an fp->int conversion? + + + // seperate OpCtrl for code readability + assign Signed = FOpCtrlE[0]; + assign Int64 = FOpCtrlE[1]; + assign IntToFp = FOpCtrlE[2]; + assign ToInt = FWriteIntE; + + // choose the ouptut format depending on the opperation + // - fp -> fp: OpCtrl contains the percision of the output + // - int -> fp: FmtE contains the percision of the output + assign OutFmt = IntToFp ? FmtE : (FOpCtrlE[1:0] == `FMT); + + /////////////////////////////////////////////////////////////////////////// + // negation + /////////////////////////////////////////////////////////////////////////// + // negate the input if the input is a negitive singed integer + // - remove leading ones if the input is a unsigned 32-bit integer + // + // Negitive input + // 64-bit input : negate the input + // 32-bit input : trim to 32-bits and negate the input + // Positive input + // 64-bit input : do nothing + // 32-bit input : trim to 32-bits + + assign PosInt = ResSgn ? Int64 ? -ForwardedSrcAE : {{`XLEN-32{1'b0}}, -ForwardedSrcAE[31:0]} : + Int64 ? ForwardedSrcAE : {{`XLEN-32{1'b0}}, ForwardedSrcAE[31:0]}; + + /////////////////////////////////////////////////////////////////////////// + // lzc + /////////////////////////////////////////////////////////////////////////// + + // choose the input to the leading zero counter i.e. priority encoder + // int -> fp : | positive integer | 00000... (if needed) | + // fp -> fp : | fraction | 00000... (if needed) | + assign LzcIn = IntToFp ? {PosInt, {`LGLEN-`XLEN{1'b0}}} : // I->F + {XManE[`NF-1:0], {`LGLEN-`NF{1'b0}}}; // F->F + + // lglen is the largest possible value of ZeroCnt (NF or XLEN) hence normcnt must be log2(lglen) bits + logic [$clog2(`LGLEN):0] i, ZeroCnt; + always_comb begin + i = 0; + while (~LzcIn[`LGLEN-1-i] & i <= `LGLEN-1) i = i+1; // search for leading one + ZeroCnt = i; + end + + + /////////////////////////////////////////////////////////////////////////// + // shifter + /////////////////////////////////////////////////////////////////////////// + // F->F shift so the fraction is not denormalized + // Large->Small Denrom -> Norm Frac: + // + // | Frac | `NF zeros| << ShiftCnt + // + // Small->Large Norm -> Denorm Frac: + // - shift right so that the new-bias exponet = 1 + // - so shift right by new-bias - 1 exponent + // - ie shift left by NF - 1 + new-bias exponent (if this is negitive then 0 is selected as a result later) + // - new-bias exponent is negitive + // + // | `NF-1 zeros |1| Frac | << NF + new-bias exponent + // | keep | + // + // Int -> Fp : + // | Int | `NF zeros| << ShiftCnt + // Fp -> Int : + // | `XLEN zeros | Man | << CalcExp + + + // seclect the input to the shifter + // fp -> int: + // | `XLEN zeros | Mantissa | 0's if nessisary | + // Other problems: + // - if shifting to the right (neg CalcExp) then don't a 1 in the round bit (to prevent an incorrect plus 1 later durring rounding) + // - we do however want to keep the one in the sticky bit so set one of bits in the sticky bit area to 1 + // - ex: for the case 0010000.... (double) + // ??? -> fp: + // - if result is denormalized or underflowed then we want to normalize the result: + // | `NF zeros | Mantissa | 0's if nessisary | + // - otherwise: + // | lzcIn | 0's if nessisary | + assign ShiftIn = ToInt ? {{`XLEN{1'b0}}, XManE[`NF]&~CalcExp[`NE], XManE[`NF-1]|(CalcExp[`NE]&XManE[`NF]), XManE[`NF-2:0], {`LGLEN-`XLEN{1'b0}}} : + ResDenormUf ? {{`NF-1{1'b0}}, XManE, {`LGLEN-`NF+1{1'b0}}} : {LzcIn, {`NF+1{1'b0}}}; +// kill the shift if it's negitive + // select the amount to shift by + // fp -> int: + // - shift left by CalcExp - essentially shifting until the unbiased exponent = 0 + // - don't shift if supposed to shift right (underflowed or denorm input) + // denormalized/undeflowed result fp -> fp: + // - shift left by NF-1+CalcExp - to shift till the biased expoenent is 0 + // ??? -> fp: + // - shift left by ZeroCnt+1 - to shift till the result is normalized + // - only shift fp -> fp if the intital value is denormalized + // - this is a problem because the input to the lzc was the fraction rather than the mantissa + // - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true? + assign ShiftAmt = ToInt ? CalcExp[$clog2(`LGLEN):0]&{$clog2(`LGLEN)+1{~CalcExp[`NE]}} : + ResDenormUf&~IntToFp ? ($clog2(`LGLEN)+1)'(`NF-1)+CalcExp[$clog2(`LGLEN):0] : (ZeroCnt+1)&{$clog2(`LGLEN)+1{XOrigDenormE|IntToFp}}; + + // shift + assign Shifted = ShiftIn << ShiftAmt; + + /////////////////////////////////////////////////////////////////////////// + // exp calculations + /////////////////////////////////////////////////////////////////////////// + // fp -> int + // CalcExp = 1 - largest bias + 1 - + + + // *** possible optimizaations: + // - if subtracting exp by bias only the msb needs a full adder, the rest can be HA - dunno how to implement this for synth + // - Smaller exp -> Larger Exp can be calculated with: *** can use in Other units??? FMA??? insert this thing in later + // Exp if in range: {~Exp[SNE-1], Exp[SNE-2:0]} + // Exp in range if: Exp[SNE-1] = 1 & Exp[LNE-2:SNE] = 1111... & Exp[LNE-1] = 0 | Exp[SNE-1] = 0 & Exp[LNE-2:SNE] = 000... & Exp[LNE-1] = 1 + // i.e.: &Exp[LNE-2:SNE-1] xor Exp[LNE-1] + // Too big if: Exp[LNE-1] = 1 + // Too small if: none of the above + + // Select the bias of the output + // fp -> int : select 1 + // ??? -> fp : pick the new bias depending on the output format + + assign NewBias = ToInt ? (`NE-1)'(1) : OutFmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); + + // select the old exponent + // int -> fp : largest bias + XLEN + // fp -> ??? : XExp + assign OldExp = IntToFp ? (`NE)'(`BIAS)+(`NE)'(`XLEN) : XExpE; + + // calculate CalcExp + // fp -> fp : + // - XExp - Largest bias + new bias + // fp -> int : XExp + // int -> fp : largest bias + XLEN + // the -XOrigDenorm is to take into account the correction (which had a plus 1) + assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XOrigDenormE|IntToFp} - {{`NE-$clog2(`LGLEN){1'b0}}, (ZeroCnt&{$clog2(`LGLEN)+1{XOrigDenormE|IntToFp}})}; + // if result is 0 or negitive + assign ResDenormUf = (~|CalcExp | CalcExp[`NE])&~XZeroE; + assign ResNegNF = (FOpCtrlE[1:0] == `FMT) ? -`NF : -`NF1; + // if the reuslt underflows and somthing is shifted out set the sticky bit + assign ResUf = ($signed(CalcExp) < $signed({{`NE-$clog2(`NF){1'b1}}, ResNegNF}))&~XZeroE; + + + /////////////////////////////////////////////////////////////////////////// + // sign + /////////////////////////////////////////////////////////////////////////// + + assign ResSgn = IntToFp ? Int64 ? ForwardedSrcAE[`XLEN-1]&Signed : ForwardedSrcAE[31]&Signed : XSgnE; + + /////////////////////////////////////////////////////////////////////////// + // rounding + /////////////////////////////////////////////////////////////////////////// + + // round to nearest even + // {Round, Sticky} + // 0x - do nothing + // 10 - tie - Plus1 if result is odd (LSBNormSum = 1) + // 11 - Plus1 + + // round to zero - do nothing + + // round to -infinity - Plus1 if negative + + // round to infinity - Plus1 if positive + + // round to nearest max magnitude + // {Guard, Round, Sticky} + // 0x - do nothing + // 1x - Plus1 + + // ResUf is used when a fp->fp result underflows but all the bits get shifted out, leaving nothing for the sticky bit + assign Sticky = ToInt ? |Shifted[`LGLEN+`NF-`XLEN-1:0] : + (OutFmt ? |Shifted[`LGLEN+`NF-`NF-1:0] : |Shifted[`LGLEN+`NF-`NF1-1:0])|ResUf; + assign Round = ToInt ? Shifted[`LGLEN+`NF-`XLEN] : + OutFmt ? Shifted[`LGLEN+`NF-`NF] : |Shifted[`LGLEN+`NF-`NF1]; + assign LSBFrac = ToInt ? Shifted[`LGLEN+`NF-`XLEN+1] : + OutFmt ? Shifted[`LGLEN+`NF-`NF+1] : Shifted[`LGLEN+`NF-`NF1+1]; + + + always_comb begin // ***remove guard bit + // Determine if you add 1 + case (FrmE) + 3'b000: CalcPlus1 = Round & (Sticky | LSBFrac);//round to nearest even + 3'b001: CalcPlus1 = 0;//round to zero + 3'b010: CalcPlus1 = ResSgn;//round down + 3'b011: CalcPlus1 = ~ResSgn;//round up + 3'b100: CalcPlus1 = Round;//round to nearest max magnitude + default: CalcPlus1 = 1'bx; + endcase + end + assign Plus1 = CalcPlus1&(Round|Sticky); + assign ShiftedPlus1 = OutFmt ? {{`FLEN-1{1'b0}},Plus1} : {{`NE+`NF1{1'b0}}, Plus1, {`FLEN-`NE-`NF1-1{1'b0}}}; + + // kill calcExp if the result is denormalized + assign {FullResExp, ResFrac} = {CalcExp&{`NE+1{~ResDenormUf}}, Shifted[`LGLEN+`NF:`LGLEN+`NF+1-`NF]} + ShiftedPlus1; + assign ResExp = FullResExp[`NE-1:0]; + /////////////////////////////////////////////////////////////////////////// + // flags + /////////////////////////////////////////////////////////////////////////// + + // calculate the flags + // dont set underflow overflow or inexact flags if result is NaN + assign MaxExp = ToInt ? Int64 ? 65 : 33 : + OutFmt ? {`NE{1'b1}} : {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}}; + // if the exponent is lager or equal to the maximum and it's not negitive + // F->F if the input is inf then the output is also Inf ie exact, so dont set the underflow flag + + // if the result exponent is larger then the maximum possible exponent + // | and the exponent is positive + // | | and the input is not NaN or Infinity + // | | | + assign Overflow = ((ResExp >= MaxExp)&~CalcExp[`NE]&~(XNaNE|XInfE)); + // only set the underflow flag if not-exact + // set the underflow flag if the result is denomal or underflowed + // can't underflow durring to integer conversions + + // if the result is denormalized or underflowed + // | and the result did not round into normal values + // | | and the result is not exact + // | | | and the result isn't NaN + // | | | | + assign Underflow = ResDenormUf & ~(ResExp==1 & CalcExp == 0) & (Sticky|Round)&~(XNaNE); + // we are using the IEEE convertToIntegerExact opperations (rather then the exact ones) which do singal the inexact flag + // if there were bits thrown away + // | if overflowed or underflowed + // | | and if not a NaN + // | | | + assign FpInexact = (Sticky|Round|Underflow|Overflow)&(~XNaNE|IntToFp); + // if the result is too small to be represented and not 0 + // | and if the result is not invalid (outside the integer bounds) + // | | + assign IntInexact = ((CalcExp[`NE]&~XZeroE)|Sticky|Round)&~Invalid; + assign Inexact = ToInt ? IntInexact : FpInexact; + // if an input was a singaling NaN(and we're using a FP input) + assign FpInvalid = (XSNaNE&~IntToFp); + + assign NegResMSBS = Signed ? Int64 ? NegRes[`XLEN:`XLEN-1] : NegRes[32:31] : + Int64 ? NegRes[`XLEN+1:`XLEN] : NegRes[33:32]; + // if the input is NaN or infinity + // | if the integer result overflows (out of range) + // | | if the input was negitive but ouputing to a unsigned number + // | | | the result doesn't round to zero + // | | | | or the result rounds up out of bounds + // | | | | and the result didn't underflow + // | | | | | + assign IntInvalid = XNaNE|XInfE|Overflow|((XSgnE&~Signed)&(~((CalcExp[`NE]|(~|CalcExp))&~Plus1)))|(NegResMSBS[1]^NegResMSBS[0]); + // | + // or when the positive result rounds up out of range + assign Invalid = ToInt ? IntInvalid : FpInvalid; + // pack the flags together and choose the result based on the opperation + // don't set the overflow or underfolw flags if converting to integer + assign CvtFlgE = {Invalid, 1'b0, Overflow&~ToInt, Underflow&~ToInt, Inexact}; + + + /////////////////////////////////////////////////////////////////////////// + // result selection + /////////////////////////////////////////////////////////////////////////// + // when the input is zero for F->F the exponent is not calulated as 0 so combine with underflow result + + //logic [$clog2(`NF)-1:0] MinDenormExp; + //assign MinDenormExp = FOpCtrlE[1:0] == `FMT ? -`NE : -`NE1; + assign KillRes = (ResUf|(XZeroE&~IntToFp)|(~|PosInt&IntToFp)); + //assign NaNRes = FOpCtrlE[1:0] == `FMT ? {1'b0, {`NE+1{1'b1}}, (`NF-1)'(0)} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; + + if(`IEEE754) begin + assign NaNRes = FOpCtrlE[1:0] == `FMT ? {1'b0, {`NE+1{1'b1}}, XManE[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, XManE[`NF-2:`NF-`NF1]}; + end else begin + assign NaNRes = FOpCtrlE[1:0] == `FMT ? {1'b0, {`NE+1{1'b1}}, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, {`NF1-1{1'b0}}}; + end + // assign InfRes = FOpCtrlE[1:0] == `FMT ? {ResSgn, {`NE{1'b1}}, (`NF)'(0)} : {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1{1'b1}}, (`NF1)'(0)}; +// output one less then the maximum value if rounding down (RZ RU RD) +// if infinitiy output infinity + assign InfRes = FOpCtrlE[1:0] == `FMT ? ~XInfE&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {ResSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : + {ResSgn, {`NE{1'b1}}, {`NF{1'b0}}} : + ~XInfE&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : + {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1{1'b1}}, (`NF1)'(0)}; +// if RU/RD then round the underflowed result if needed +// integer zero's exponent is not calculated corresctly so go through underflow result + assign UfRes = OutFmt ? {ResSgn, (`FLEN-2)'(0), Plus1&FrmE[1]} : {{`FLEN-`LEN1{1'b1}}, ResSgn, (`LEN1-2)'(0), Plus1&FrmE[1]}; + assign Res = OutFmt ? {ResSgn, ResExp, ResFrac} : {{`FLEN-`LEN1{1'b1}}, ResSgn, ResExp[`NE1-1:0], ResFrac[`NF-1:`NF-`NF1]}; + assign CvtResE = XNaNE&~IntToFp ? NaNRes : + (XInfE|Overflow)&~IntToFp ? InfRes : + KillRes ? UfRes : + Res; + // *** probably can optimize the negation + // NaNs sould ouput the same as a positive infinity + // a 32bit unsigend result should be sign extended (as if it is not a unsigned number) + assign OfIntRes = Signed ? XSgnE&~XNaNE ? Int64 ? {1'b1, {`XLEN-1{1'b0}}} : {{`XLEN-32{1'b1}}, 1'b1, {31{1'b0}}} : // signed negitive + Int64 ? {1'b0, {`XLEN-1{1'b1}}} : {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}} : // signed positive + XSgnE&~XNaNE ? {`XLEN{1'b0}} : // unsigned negitive + {`XLEN{1'b1}};// unsigned positive + + + assign NegRes = XSgnE ? -({2'b0, Shifted[`LGLEN+`NF:`LGLEN+`NF+1-`XLEN]}+{{`XLEN+1{1'b0}},Plus1}) : {2'b0, Shifted[`LGLEN+`NF:`LGLEN+`NF+1-`XLEN]}+{{`XLEN+1{1'b0}},Plus1}; + assign CvtIntResE = Invalid ? OfIntRes : + CalcExp[`NE] ? XSgnE&Signed&Plus1 ? {{`XLEN{1'b1}}} : {{`XLEN-1{1'b0}}, Plus1} : //CalcExp has to come after invalid ***swap to actual mux at some point?? + Int64 ? NegRes[`XLEN-1:0] : {{`XLEN-32{NegRes[31]}}, NegRes[31:0]}; + +endmodule \ No newline at end of file From 5a9e3a852a6325542909fa0e297dcfe19f126993 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 25 May 2022 17:10:59 -0700 Subject: [PATCH 12/28] see commit 9042cc3c --- pipelined/testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index b40fcf365..86760487a 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -373,7 +373,7 @@ module riscvassertions; assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); - assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16"); + assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); end endmodule From 466fb71addf85c3891e4bab638e2ada6d0190e33 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 25 May 2022 17:40:57 -0700 Subject: [PATCH 13/28] added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction --- pipelined/regression/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 3daadf769..664f99648 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -46,7 +46,7 @@ configs = [ ] def getBuildrootTC(short): INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM - MAX_EXPECTED = 246000000 + MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. if short: BRcmd="vsim > {} -c < Date: Thu, 26 May 2022 16:45:28 +0000 Subject: [PATCH 14/28] Set up the divider for on-the-fly conversion --- addins/riscv-arch-test | 2 +- pipelined/srt/srt.sv | 19 ++++++++++++++++++- pipelined/srt/testbench.sv | 11 +++++++++-- 3 files changed, 28 insertions(+), 4 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99bd..307c77b26 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index bbcabccb9..c5e837180 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -47,7 +47,7 @@ module srt #(parameter Nf=52) ( input logic Int, // Choose integer inputss input logic Sqrt, // perform square root, not divide output logic rsign, - output logic [Nf-1:0] Quot, Rem, // *** later handle integers + output logic [Nf-1:0] Quot, Rem, QuotOTFC, // *** later handle integers output logic [`NE-1:0] rExp, output logic [3:0] Flags ); @@ -91,6 +91,8 @@ module srt #(parameter Nf=52) ( signcalc signcalc(.XSign, .YSign, .calcSign); srtpostproc postproc(rp, rm, Quot); + + otfc otfc(qp, qz, qm, Quot, QuotOTFC); endmodule module srtpostproc #(parameter N=52) ( @@ -210,9 +212,24 @@ module qacc #(parameter N=55) ( end */ endmodule +////////// +// otfc // +////////// + +module otfc #(parameter N=52) ( + input logic qp, qz, qm, + input logic [N-1:0] Quot, + output logic [N-1:0] QuotOTFC +); + + assign QuotOTFC = Quot; + +endmodule + ///////// // inv // ///////// + module inv(input logic [55:0] in, output logic [55:0] out); diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 08b5d0d79..022fa845f 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -44,7 +44,7 @@ module testbench; logic [51:0] afrac, bfrac; logic [10:0] aExp, bExp; logic asign, bsign; - logic [51:0] r; + logic [51:0] r, rOTFC; logic [54:0] rp, rm; // positive quotient digits // Test parameters @@ -72,7 +72,7 @@ module testbench; .SrcXFrac(afrac), .SrcYFrac(bfrac), .SrcA('0), .SrcB('0), .Fmt(2'b00), .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), - .Quot(r), .Rem(), .Flags()); + .Quot(r), .QuotOTFC(rOTFC), .Rem(), .Flags()); // Counter counter counter(clk, req, done); @@ -117,6 +117,13 @@ module testbench; $display("failed\n"); $stop; end + if (r !== rOTFC) // Check if OTFC works + begin + errors = errors+1; + $display("OTFC is %h, should be %h\n", rOTFC, r); + $display("failed/n"); + $stop; + end if (afrac === 52'hxxxxxxxxxxxxx) begin $display("%d Tests completed successfully", testnum); From a983791d6403bf2d32a54dbd96e77ec9f6f8296e Mon Sep 17 00:00:00 2001 From: DTowersM Date: Thu, 26 May 2022 19:04:21 +0000 Subject: [PATCH 15/28] fixed indent spacing (cosmetic change) --- pipelined/testbench/testbench.sv | 84 ++++++++++++++++---------------- 1 file changed, 41 insertions(+), 43 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 86760487a..fb338848c 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -87,7 +87,7 @@ logic [3:0] dummy; "arch64m": if (`M_SUPPORTED) tests = arch64m; "arch64d": if (`D_SUPPORTED) tests = arch64d; "imperas64i": tests = imperas64i; -// "imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu; + //"imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu; "imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64d": if (`D_SUPPORTED) tests = imperas64d; "imperas64m": if (`M_SUPPORTED) tests = imperas64m; @@ -110,7 +110,7 @@ logic [3:0] dummy; "arch32m": if (`M_SUPPORTED) tests = arch32m; "arch32f": if (`F_SUPPORTED) tests = arch32f; "imperas32i": tests = imperas32i; -// "imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu; + //"imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu; "imperas32f": if (`F_SUPPORTED) tests = imperas32f; "imperas32m": if (`M_SUPPORTED) tests = imperas32m; "wally32a": if (`A_SUPPORTED) tests = wally32a; @@ -183,7 +183,7 @@ logic [3:0] dummy; // read test vectors into memory pathname = tvpaths[tests[0].atoi()]; -/* if (tests[0] == `IMPERASTEST) + /* if (tests[0] == `IMPERASTEST) pathname = tvpaths[0]; else pathname = tvpaths[1]; */ memfilename = {pathname, tests[test], ".elf.memfile"}; @@ -255,7 +255,7 @@ logic [3:0] dummy; //if (signature[i] !== dut.core.lsu.dtim.ram.memory.RAM[testadr+i] & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin // ***i+1? if ((signature[i] !== '0 | signature[i+4] !== 'x)) begin -// if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin + // if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin // report errors unless they are garbage at the end of the sim // kind of hacky test for garbage right now $display("sig4 = %h ne %b", signature[i+4], signature[i+4] !== 'bx); @@ -368,7 +368,7 @@ module riscvassertions; assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); -// assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); + // assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); @@ -409,47 +409,45 @@ module DCacheFlushFSM logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0]; logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0]; logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0]; - for(index = 0; index < numlines; index++) begin - for(way = 0; way < numways; way++) begin - for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin - copyShadow #(.tagstart(tagstart), - .loglinebytelen(loglinebytelen)) - copyShadow(.clk, - .start, - .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]), - .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), - .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), - .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]), - .index(index), - .cacheWord(cacheWord), - .CacheData(CacheData[way][index][cacheWord]), - .CacheAdr(CacheAdr[way][index][cacheWord]), - .CacheTag(CacheTag[way][index][cacheWord]), - .CacheValid(CacheValid[way][index][cacheWord]), - .CacheDirty(CacheDirty[way][index][cacheWord])); - end - end + for(index = 0; index < numlines; index++) begin + for(way = 0; way < numways; way++) begin + for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin + copyShadow #(.tagstart(tagstart), + .loglinebytelen(loglinebytelen)) + copyShadow(.clk, + .start, + .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]), + .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), + .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), + .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]), + .index(index), + .cacheWord(cacheWord), + .CacheData(CacheData[way][index][cacheWord]), + .CacheAdr(CacheAdr[way][index][cacheWord]), + .CacheTag(CacheTag[way][index][cacheWord]), + .CacheValid(CacheValid[way][index][cacheWord]), + .CacheDirty(CacheDirty[way][index][cacheWord])); + end end + end - integer i, j, k; + integer i, j, k; - always @(posedge clk) begin - if (start) begin #1 - #1 - for(i = 0; i < numlines; i++) begin - for(j = 0; j < numways; j++) begin - for(k = 0; k < numwords; k++) begin - if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin - ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k]; - end - end - end - end - end - end - - - end + always @(posedge clk) begin + if (start) begin #1 + #1 + for(i = 0; i < numlines; i++) begin + for(j = 0; j < numways; j++) begin + for(k = 0; k < numwords; k++) begin + if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin + ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k]; + end + end + end + end + end + end + end flop #(1) doneReg(.clk, .d(start), .q(done)); endmodule From 550c4d380c2c9901eeecfa671f2a63e4069dbe15 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 26 May 2022 20:48:22 +0000 Subject: [PATCH 16/28] fcvt.sv paramaterized --- pipelined/config/rv64fp/wally-config.vh | 4 +- pipelined/src/fpu/fcvt.sv | 621 ++++++++++++++++++++---- pipelined/testbench/testbench-fp.sv | 24 +- pipelined/testbench/tests-fp.vh | 56 +-- 4 files changed, 573 insertions(+), 132 deletions(-) diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index e88b012aa..36cda4d91 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -39,12 +39,12 @@ // MISA RISC-V configuration per specification //16 - quad 3 - double 5 - single -`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 0 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 +`define ZFH_SUPPORTED 1 /// Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index 9195bc893..55e6706c5 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -82,7 +82,11 @@ module fcvt ( // choose the ouptut format depending on the opperation // - fp -> fp: OpCtrl contains the percision of the output // - int -> fp: FmtE contains the percision of the output - assign OutFmt = IntToFp ? FmtE : (FOpCtrlE[1:0] == `FMT); + if (`FPSIZES == 2) + assign OutFmt = IntToFp ? FmtE : (FOpCtrlE[1:0] == `FMT); + else if (`FPSIZES == 3 | `FPSIZES == 4) + assign OutFmt = IntToFp ? FmtE : FOpCtrlE[1:0]; + /////////////////////////////////////////////////////////////////////////// // negation @@ -108,7 +112,7 @@ module fcvt ( // int -> fp : | positive integer | 00000... (if needed) | // fp -> fp : | fraction | 00000... (if needed) | assign LzcIn = IntToFp ? {PosInt, {`LGLEN-`XLEN{1'b0}}} : // I->F - {XManE[`NF-1:0], {`LGLEN-`NF{1'b0}}}; // F->F + {XManE[`NF-1:0], {`LGLEN-`NF{1'b0}}}; // F->F // lglen is the largest possible value of ZeroCnt (NF or XLEN) hence normcnt must be log2(lglen) bits logic [$clog2(`LGLEN):0] i, ZeroCnt; @@ -122,25 +126,6 @@ module fcvt ( /////////////////////////////////////////////////////////////////////////// // shifter /////////////////////////////////////////////////////////////////////////// - // F->F shift so the fraction is not denormalized - // Large->Small Denrom -> Norm Frac: - // - // | Frac | `NF zeros| << ShiftCnt - // - // Small->Large Norm -> Denorm Frac: - // - shift right so that the new-bias exponet = 1 - // - so shift right by new-bias - 1 exponent - // - ie shift left by NF - 1 + new-bias exponent (if this is negitive then 0 is selected as a result later) - // - new-bias exponent is negitive - // - // | `NF-1 zeros |1| Frac | << NF + new-bias exponent - // | keep | - // - // Int -> Fp : - // | Int | `NF zeros| << ShiftCnt - // Fp -> Int : - // | `XLEN zeros | Man | << CalcExp - // seclect the input to the shifter // fp -> int: @@ -150,12 +135,13 @@ module fcvt ( // - we do however want to keep the one in the sticky bit so set one of bits in the sticky bit area to 1 // - ex: for the case 0010000.... (double) // ??? -> fp: - // - if result is denormalized or underflowed then we want to normalize the result: - // | `NF zeros | Mantissa | 0's if nessisary | + // - if result is denormalized or underflowed then we want to shift right i.e. shift right then shift left: + // | `NF-1 zeros | Mantissa | 0's if nessisary | // - otherwise: // | lzcIn | 0's if nessisary | assign ShiftIn = ToInt ? {{`XLEN{1'b0}}, XManE[`NF]&~CalcExp[`NE], XManE[`NF-1]|(CalcExp[`NE]&XManE[`NF]), XManE[`NF-2:0], {`LGLEN-`XLEN{1'b0}}} : - ResDenormUf ? {{`NF-1{1'b0}}, XManE, {`LGLEN-`NF+1{1'b0}}} : {LzcIn, {`NF+1{1'b0}}}; + ResDenormUf ? {{`NF-1{1'b0}}, XManE, {`LGLEN-`NF+1{1'b0}}} : + {LzcIn, {`NF+1{1'b0}}}; // kill the shift if it's negitive // select the amount to shift by // fp -> int: @@ -169,16 +155,49 @@ module fcvt ( // - this is a problem because the input to the lzc was the fraction rather than the mantissa // - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true? assign ShiftAmt = ToInt ? CalcExp[$clog2(`LGLEN):0]&{$clog2(`LGLEN)+1{~CalcExp[`NE]}} : - ResDenormUf&~IntToFp ? ($clog2(`LGLEN)+1)'(`NF-1)+CalcExp[$clog2(`LGLEN):0] : (ZeroCnt+1)&{$clog2(`LGLEN)+1{XOrigDenormE|IntToFp}}; + ResDenormUf&~IntToFp ? ($clog2(`LGLEN)+1)'(`NF-1)+CalcExp[$clog2(`LGLEN):0] : + (ZeroCnt+1)&{$clog2(`LGLEN)+1{XOrigDenormE|IntToFp}}; // shift + // fp -> int: | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp + // process: + // - start - CalcExp = 1 + XExp - Largest Bias + // | `XLEN zeros | Mantissa | 0's if nessisary | + // + // - shift left 1 (1) + // | `XLEN-1 zeros |bit| frac | 0's if nessisary | + // . <- binary point + // + // - shift left till unbiased exponent is 0 (XExp - Largest Bias) + // | 0's | Mantissa | 0's if nessisary | + // | keep | + // + // fp -> fp: + // - if result is denormalized or underflowed: + // | `NF-1 zeros | Mantissa | 0's if nessisary | << NF+CalcExp-1 + // process: + // - start + // | mantissa | 0's | + // + // - shift right by NF-1 (NF-1) + // | `NF-1 zeros | mantissa | 0's | + // + // - shift left by CalcExp = XExp - Largest bias + new bias + // | 0's | mantissa | 0's | + // | keep | + // + // - if the input is denormalized: + // | lzcIn | 0's if nessisary | << ZeroCnt+1 + // - plus 1 to shift out the first 1 + // + // int -> fp: | lzcIn | 0's if nessisary | << ZeroCnt+1 + // - plus 1 to shift out the first 1 + assign Shifted = ShiftIn << ShiftAmt; /////////////////////////////////////////////////////////////////////////// // exp calculations /////////////////////////////////////////////////////////////////////////// - // fp -> int - // CalcExp = 1 - largest bias + 1 - // *** possible optimizaations: @@ -192,10 +211,35 @@ module fcvt ( // Select the bias of the output // fp -> int : select 1 - // ??? -> fp : pick the new bias depending on the output format + // ??? -> fp : pick the new bias depending on the output format + if (`FPSIZES == 1) begin + assign NewBias = ToInt ? (`NE-1)'(1) : (`NE-1)'(`BIAS); - assign NewBias = ToInt ? (`NE-1)'(1) : OutFmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); + end else if (`FPSIZES == 2) begin + assign NewBias = ToInt ? (`NE-1)'(1) : OutFmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); + end else if (`FPSIZES == 3) begin + logic [`NE-2:0] NewBiasToFp; + always_comb + case (OutFmt) + `FMT: NewBiasToFp = (`NE-1)'(`BIAS); + `FMT1: NewBiasToFp = (`NE-1)'(`BIAS1); + `FMT2: NewBiasToFp = (`NE-1)'(`BIAS2); + default: NewBiasToFp = 1'bx; + endcase + assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; + + end else if (`FPSIZES == 4) begin + logic [`NE-2:0] NewBiasToFp; + always_comb + case (OutFmt) + 2'h3: NewBiasToFp = (`NE-1)'(`Q_BIAS); + 2'h1: NewBiasToFp = (`NE-1)'(`D_BIAS); + 2'h0: NewBiasToFp = (`NE-1)'(`S_BIAS); + 2'h2: NewBiasToFp = (`NE-1)'(`H_BIAS); + endcase + assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; + end // select the old exponent // int -> fp : largest bias + XLEN // fp -> ??? : XExp @@ -203,22 +247,76 @@ module fcvt ( // calculate CalcExp // fp -> fp : - // - XExp - Largest bias + new bias - // fp -> int : XExp - // int -> fp : largest bias + XLEN - // the -XOrigDenorm is to take into account the correction (which had a plus 1) + // - XExp - Largest bias + new bias - (ZeroCnt+1) + // only do ^ if the input was denormalized + // - convert the expoenent to the final preciaion (Exp - oldBias + newBias) + // - correct the expoent when there is a normalization shift ( + ZeroCnt+1) + // fp -> int : XExp - Largest Bias + 1 - (ZeroCnt+1) + // | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp + // process: + // - start + // | `XLEN zeros | Mantissa | 0's if nessisary | + // + // - shift left 1 (1) + // | `XLEN-1 zeros |bit| frac | 0's if nessisary | + // . <- binary point + // + // - shift left till unbiased exponent is 0 (XExp - Largest Bias) + // | 0's | Mantissa | 0's if nessisary | + // | keep | + // + // - if the input is denormalized then we dont shift... so the "- (ZeroCnt+1)" is just leftovers from other options + // int -> fp : largest bias XLEN - Largest bias + new bias - 1 - ZeroCnt = XLEN + NewBias - 1 - ZeroCnt + // Process: + // - shifted right by XLEN (XLEN) + // - shift left to normilize (-1-ZeroCnt) + // - newBias to make the biased exponent + // assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XOrigDenormE|IntToFp} - {{`NE-$clog2(`LGLEN){1'b0}}, (ZeroCnt&{$clog2(`LGLEN)+1{XOrigDenormE|IntToFp}})}; - // if result is 0 or negitive - assign ResDenormUf = (~|CalcExp | CalcExp[`NE])&~XZeroE; - assign ResNegNF = (FOpCtrlE[1:0] == `FMT) ? -`NF : -`NF1; - // if the reuslt underflows and somthing is shifted out set the sticky bit - assign ResUf = ($signed(CalcExp) < $signed({{`NE-$clog2(`NF){1'b1}}, ResNegNF}))&~XZeroE; + // find if the result is dnormal or underflows + // - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) + // - can't underflow an integer to Fp conversion + assign ResDenormUf = (~|CalcExp | CalcExp[`NE])&~XZeroE&~IntToFp; + // choose the negative of the fraction size + if (`FPSIZES == 1) begin + assign ResNegNF = -`NF; + + end else if (`FPSIZES == 2) begin + assign ResNegNF = OutFmt ? -`NF : -`NF1; + + end else if (`FPSIZES == 3) begin + always_comb + case (OutFmt) + `FMT: ResNegNF = -`NF; + `FMT1: ResNegNF = -`NF1; + `FMT2: ResNegNF = -`NF2; + default: ResNegNF = 1'bx; + endcase + + end else if (`FPSIZES == 4) begin + always_comb + case (OutFmt) + 2'h3: ResNegNF = -`Q_NF; + 2'h1: ResNegNF = -`D_NF; + 2'h0: ResNegNF = -`S_NF; + 2'h2: ResNegNF = -`H_NF; + endcase + end + // determine if the result underflows ??? -> fp + // - if the first 1 is shifted out of the result then the result underflows + // - can't underflow an integer to fp conversions + assign ResUf = ($signed(CalcExp) < $signed({{`NE-$clog2(`NF){1'b1}}, ResNegNF}))&~XZeroE&~IntToFp; /////////////////////////////////////////////////////////////////////////// // sign /////////////////////////////////////////////////////////////////////////// + // determine the sign of the result + // - if int -> fp + // - if 64-bit : check the msb of the 64-bit integer input and if it's signed + // - if 32-bit : check the msb of the 32-bit integer input and if it's signed + // - otherwise: the floating point input's sign assign ResSgn = IntToFp ? Int64 ? ForwardedSrcAE[`XLEN-1]&Signed : ForwardedSrcAE[31]&Signed : XSgnE; /////////////////////////////////////////////////////////////////////////// @@ -241,17 +339,80 @@ module fcvt ( // {Guard, Round, Sticky} // 0x - do nothing // 1x - Plus1 + // ResUf is used when a fp->fp result underflows but all the bits get shifted out, which leaves nothing for the sticky bit + if (`FPSIZES == 1) begin + assign Sticky = ToInt ? |Shifted[`LGLEN+`NF-`XLEN-1:0] : |Shifted[`LGLEN+`NF-`NF-1:0]|ResUf; + assign Round = ToInt ? Shifted[`LGLEN+`NF-`XLEN] : Shifted[`LGLEN+`NF-`NF]; + assign LSBFrac = ToInt ? Shifted[`LGLEN+`NF-`XLEN+1] : Shifted[`LGLEN+`NF-`NF+1]; - // ResUf is used when a fp->fp result underflows but all the bits get shifted out, leaving nothing for the sticky bit - assign Sticky = ToInt ? |Shifted[`LGLEN+`NF-`XLEN-1:0] : - (OutFmt ? |Shifted[`LGLEN+`NF-`NF-1:0] : |Shifted[`LGLEN+`NF-`NF1-1:0])|ResUf; - assign Round = ToInt ? Shifted[`LGLEN+`NF-`XLEN] : - OutFmt ? Shifted[`LGLEN+`NF-`NF] : |Shifted[`LGLEN+`NF-`NF1]; - assign LSBFrac = ToInt ? Shifted[`LGLEN+`NF-`XLEN+1] : - OutFmt ? Shifted[`LGLEN+`NF-`NF+1] : Shifted[`LGLEN+`NF-`NF1+1]; + end else if (`FPSIZES == 2) begin + assign Sticky = ToInt ? |Shifted[`LGLEN+`NF-`XLEN-1:0] : + (OutFmt ? |Shifted[`LGLEN+`NF-`NF-1:0] : |Shifted[`LGLEN+`NF-`NF1-1:0])|ResUf; + assign Round = ToInt ? Shifted[`LGLEN+`NF-`XLEN] : + OutFmt ? Shifted[`LGLEN+`NF-`NF] : Shifted[`LGLEN+`NF-`NF1]; + assign LSBFrac = ToInt ? Shifted[`LGLEN+`NF-`XLEN+1] : + OutFmt ? Shifted[`LGLEN+`NF-`NF+1] : Shifted[`LGLEN+`NF-`NF1+1]; + end else if (`FPSIZES == 3) begin + logic ToFpSticky, ToFpRound, ToFpLSBFrac; + always_comb + case (OutFmt) + `FMT: begin + ToFpSticky = |Shifted[`LGLEN+`NF-`NF-1:0]; + ToFpRound = Shifted[`LGLEN+`NF-`NF]; + ToFpLSBFrac = Shifted[`LGLEN+`NF-`NF+1]; + end + `FMT1: begin + ToFpSticky = |Shifted[`LGLEN+`NF-`NF1-1:0]; + ToFpRound = Shifted[`LGLEN+`NF-`NF1]; + ToFpLSBFrac = Shifted[`LGLEN+`NF-`NF1+1]; + end + `FMT2: begin + ToFpSticky = |Shifted[`LGLEN+`NF-`NF2-1:0]; + ToFpRound = Shifted[`LGLEN+`NF-`NF2]; + ToFpLSBFrac = Shifted[`LGLEN+`NF-`NF2+1]; + end + default: begin + ToFpSticky = 1'bx; + ToFpRound = 1'bx; + ToFpLSBFrac = 1'bx; + end + endcase + assign Sticky = ToInt ? |Shifted[`LGLEN+`NF-`XLEN-1:0] : ToFpSticky|ResUf; + assign Round = ToInt ? Shifted[`LGLEN+`NF-`XLEN] : ToFpRound; + assign LSBFrac = ToInt ? Shifted[`LGLEN+`NF-`XLEN+1] : ToFpLSBFrac; - always_comb begin // ***remove guard bit + end else if (`FPSIZES == 4) begin + logic ToFpSticky, ToFpRound, ToFpLSBFrac; + always_comb + case (OutFmt) + 2'h3: begin + ToFpSticky = |Shifted[`LGLEN+`Q_NF-`Q_NF-1:0]; + ToFpRound = Shifted[`LGLEN+`Q_NF-`Q_NF]; + ToFpLSBFrac = Shifted[`LGLEN+`Q_NF-`Q_NF+1]; + end + 2'h1: begin + ToFpSticky = |Shifted[`LGLEN+`Q_NF-`D_NF-1:0]; + ToFpRound = Shifted[`LGLEN+`Q_NF-`D_NF]; + ToFpLSBFrac = Shifted[`LGLEN+`Q_NF-`D_NF+1]; + end + 2'h0: begin + ToFpSticky = |Shifted[`LGLEN+`Q_NF-`S_NF-1:0]; + ToFpRound = Shifted[`LGLEN+`Q_NF-`S_NF]; + ToFpLSBFrac = Shifted[`LGLEN+`Q_NF-`S_NF+1]; + end + 2'h2: begin + ToFpSticky = |Shifted[`LGLEN+`Q_NF-`H_NF-1:0]; + ToFpRound = Shifted[`LGLEN+`Q_NF-`H_NF]; + ToFpLSBFrac = Shifted[`LGLEN+`Q_NF-`H_NF+1]; + end + endcase + assign Sticky = ToInt ? |Shifted[`LGLEN+`NF-`XLEN-1:0] : ToFpSticky|ResUf; + assign Round = ToInt ? Shifted[`LGLEN+`NF-`XLEN] : ToFpRound; + assign LSBFrac = ToInt ? Shifted[`LGLEN+`NF-`XLEN+1] : ToFpLSBFrac; + end + + always_comb // Determine if you add 1 case (FrmE) 3'b000: CalcPlus1 = Round & (Sticky | LSBFrac);//round to nearest even @@ -261,32 +422,98 @@ module fcvt ( 3'b100: CalcPlus1 = Round;//round to nearest max magnitude default: CalcPlus1 = 1'bx; endcase - end - assign Plus1 = CalcPlus1&(Round|Sticky); - assign ShiftedPlus1 = OutFmt ? {{`FLEN-1{1'b0}},Plus1} : {{`NE+`NF1{1'b0}}, Plus1, {`FLEN-`NE-`NF1-1{1'b0}}}; + // dont round if exact + assign Plus1 = CalcPlus1&(Round|Sticky); + + // shift the 1 to the propper position for rounding + // - dont round it converting to integer + if (`FPSIZES == 1) begin + assign ShiftedPlus1 = {{`FLEN-1{1'b0}},Plus1&~ToInt}; + + end else if (`FPSIZES == 2) begin + assign ShiftedPlus1 = OutFmt ? {{`FLEN-1{1'b0}},Plus1&~ToInt} : {{`NE+`NF1{1'b0}}, Plus1&~ToInt, {`FLEN-`NE-`NF1-1{1'b0}}}; + + end else if (`FPSIZES == 3) begin + always_comb + case (OutFmt) + `FMT: ShiftedPlus1 = {{`FLEN-1{1'b0}},Plus1&~ToInt}; + `FMT1: ShiftedPlus1 = {{`NE+`NF1{1'b0}}, Plus1&~ToInt, {`FLEN-`NE-`NF1-1{1'b0}}}; + `FMT2: ShiftedPlus1 = {{`NE+`NF2{1'b0}}, Plus1&~ToInt, {`FLEN-`NE-`NF2-1{1'b0}}}; + default: ShiftedPlus1 = 0; + endcase + + end else if (`FPSIZES == 4) begin + always_comb + case (OutFmt) + 2'h3: ShiftedPlus1 = {{`Q_LEN-1{1'b0}},Plus1&~ToInt}; + 2'h1: ShiftedPlus1 = {{`Q_NE+`D_NF{1'b0}}, Plus1&~ToInt, {`Q_LEN-`Q_NE-`D_NF-1{1'b0}}}; + 2'h0: ShiftedPlus1 = {{`Q_NE+`S_NF{1'b0}}, Plus1&~ToInt, {`Q_LEN-`Q_NE-`S_NF-1{1'b0}}}; + 2'h2: ShiftedPlus1 = {{`Q_NE+`H_NF{1'b0}}, Plus1&~ToInt, {`Q_LEN-`Q_NE-`H_NF-1{1'b0}}}; + endcase + end // kill calcExp if the result is denormalized assign {FullResExp, ResFrac} = {CalcExp&{`NE+1{~ResDenormUf}}, Shifted[`LGLEN+`NF:`LGLEN+`NF+1-`NF]} + ShiftedPlus1; + // trim the result's expoent to size assign ResExp = FullResExp[`NE-1:0]; /////////////////////////////////////////////////////////////////////////// // flags /////////////////////////////////////////////////////////////////////////// // calculate the flags - // dont set underflow overflow or inexact flags if result is NaN - assign MaxExp = ToInt ? Int64 ? 65 : 33 : - OutFmt ? {`NE{1'b1}} : {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}}; - // if the exponent is lager or equal to the maximum and it's not negitive - // F->F if the input is inf then the output is also Inf ie exact, so dont set the underflow flag + + // find the maximum exponent (the exponent and larger overflows) + if (`FPSIZES == 1) begin + assign MaxExp = ToInt ? Int64 ? 65 : 33 : {`NE{1'b1}}; + + end else if (`FPSIZES == 2) begin + assign MaxExp = ToInt ? Int64 ? 65 : 33 : + OutFmt ? {`NE{1'b1}} : {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}}; + + end else if (`FPSIZES == 3) begin + logic [`NE-1:0] MaxExpFp; + always_comb + case (OutFmt) + `FMT: begin + MaxExpFp = {`NE{1'b1}}; + end + `FMT1: begin + MaxExpFp = {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}}; + end + `FMT2: begin + MaxExpFp = {{`NE-`NE2{1'b0}}, {`NE2{1'b1}}}; + end + default: begin + MaxExpFp = 1'bx; + end + endcase + assign MaxExp = ToInt ? Int64 ? 65 : 33 : MaxExpFp; + + end else if (`FPSIZES == 4) begin + logic [`NE-1:0] MaxExpFp; + always_comb + case (OutFmt) + 2'h3: begin + MaxExpFp = {`Q_NE{1'b1}}; + end + 2'h1: begin + MaxExpFp = {{`Q_NE-`D_NE{1'b0}}, {`D_NE{1'b1}}}; + end + 2'h0: begin + MaxExpFp = {{`Q_NE-`S_NE{1'b0}}, {`S_NE{1'b1}}}; + end + 2'h2: begin + MaxExpFp = {{`Q_NE-`H_NE{1'b0}}, {`H_NE{1'b1}}}; + end + endcase + assign MaxExp = ToInt ? Int64 ? 65 : 33 : MaxExpFp; + end // if the result exponent is larger then the maximum possible exponent // | and the exponent is positive // | | and the input is not NaN or Infinity // | | | - assign Overflow = ((ResExp >= MaxExp)&~CalcExp[`NE]&~(XNaNE|XInfE)); - // only set the underflow flag if not-exact - // set the underflow flag if the result is denomal or underflowed - // can't underflow durring to integer conversions + assign Overflow = ((ResExp >= MaxExp)&~CalcExp[`NE]&(~(XNaNE|XInfE)|IntToFp)); // if the result is denormalized or underflowed // | and the result did not round into normal values @@ -294,18 +521,24 @@ module fcvt ( // | | | and the result isn't NaN // | | | | assign Underflow = ResDenormUf & ~(ResExp==1 & CalcExp == 0) & (Sticky|Round)&~(XNaNE); + // we are using the IEEE convertToIntegerExact opperations (rather then the exact ones) which do singal the inexact flag // if there were bits thrown away // | if overflowed or underflowed // | | and if not a NaN // | | | assign FpInexact = (Sticky|Round|Underflow|Overflow)&(~XNaNE|IntToFp); + // if the result is too small to be represented and not 0 // | and if the result is not invalid (outside the integer bounds) // | | assign IntInexact = ((CalcExp[`NE]&~XZeroE)|Sticky|Round)&~Invalid; + + // select the inexact flag to output assign Inexact = ToInt ? IntInexact : FpInexact; + // if an input was a singaling NaN(and we're using a FP input) + // | assign FpInvalid = (XSNaNE&~IntToFp); assign NegResMSBS = Signed ? Int64 ? NegRes[`XLEN:`XLEN-1] : NegRes[32:31] : @@ -320,54 +553,262 @@ module fcvt ( assign IntInvalid = XNaNE|XInfE|Overflow|((XSgnE&~Signed)&(~((CalcExp[`NE]|(~|CalcExp))&~Plus1)))|(NegResMSBS[1]^NegResMSBS[0]); // | // or when the positive result rounds up out of range + // select the inexact flag to output assign Invalid = ToInt ? IntInvalid : FpInvalid; - // pack the flags together and choose the result based on the opperation - // don't set the overflow or underfolw flags if converting to integer + // pack the flags together + // - fp -> int does not set the overflow or underflow flags assign CvtFlgE = {Invalid, 1'b0, Overflow&~ToInt, Underflow&~ToInt, Inexact}; /////////////////////////////////////////////////////////////////////////// // result selection /////////////////////////////////////////////////////////////////////////// - // when the input is zero for F->F the exponent is not calulated as 0 so combine with underflow result - //logic [$clog2(`NF)-1:0] MinDenormExp; - //assign MinDenormExp = FOpCtrlE[1:0] == `FMT ? -`NE : -`NE1; + // determine if you shoould kill the result + // - do so if the result underflows, is zero (the exp doesnt calculate correctly). or the integer input is 0 + // - dont set to zero if fp input is zero but not using the fp input + // - dont set to zero if int input is zero but not using the int input assign KillRes = (ResUf|(XZeroE&~IntToFp)|(~|PosInt&IntToFp)); - //assign NaNRes = FOpCtrlE[1:0] == `FMT ? {1'b0, {`NE+1{1'b1}}, (`NF-1)'(0)} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, (`NF1-1)'(0)}; - - if(`IEEE754) begin - assign NaNRes = FOpCtrlE[1:0] == `FMT ? {1'b0, {`NE+1{1'b1}}, XManE[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, XManE[`NF-2:`NF-`NF1]}; - end else begin - assign NaNRes = FOpCtrlE[1:0] == `FMT ? {1'b0, {`NE+1{1'b1}}, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, {`NF1-1{1'b0}}}; + + if (`FPSIZES == 1) begin + // IEEE sends a payload while Riscv says to send a canonical quiet NaN + if(`IEEE754) begin + assign NaNRes = {1'b0, {`NE+1{1'b1}}, XManE[`NF-2:0]}; + end else begin + assign NaNRes = {1'b0, {`NE+1{1'b1}}, {`NF-1{1'b0}}}; + end + // determine the infinity result + // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - otherwise: output infinity with the correct sign + // - kill the infinity singal if the input isn't fp + assign InfRes = (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {ResSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {ResSgn, {`NE{1'b1}}, {`NF{1'b0}}}; + + // result for when the result is killed i.e. underflowes + // - output a rounded 0 with the correct sign + assign UfRes = {ResSgn, (`FLEN-2)'(0), Plus1&FrmE[1]}; + + // format the result - NaN box single precision (put 1's in the unused msbs) + assign Res = {ResSgn, ResExp, ResFrac}; + + + end else if (`FPSIZES == 2) begin + // IEEE sends a payload while Riscv says to send a canonical quiet NaN + if(`IEEE754) begin + assign NaNRes = OutFmt ? {1'b0, {`NE+1{1'b1}}, XManE[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, XManE[`NF-2:`NF-`NF1]}; + end else begin + assign NaNRes = OutFmt ? {1'b0, {`NE+1{1'b1}}, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, {`NF1-1{1'b0}}}; + end + // determine the infinity result + // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - otherwise: output infinity with the correct sign + // - kill the infinity singal if the input isn't fp + assign InfRes = OutFmt ? (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {ResSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : + {ResSgn, {`NE{1'b1}}, {`NF{1'b0}}} : + (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : + {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1{1'b1}}, (`NF1)'(0)}; + + // result for when the result is killed i.e. underflowes + // - output a rounded 0 with the correct sign + assign UfRes = OutFmt ? {ResSgn, (`FLEN-2)'(0), Plus1&FrmE[1]} : {{`FLEN-`LEN1{1'b1}}, ResSgn, (`LEN1-2)'(0), Plus1&FrmE[1]}; + + // format the result - NaN box single precision (put 1's in the unused msbs) + assign Res = OutFmt ? {ResSgn, ResExp, ResFrac} : {{`FLEN-`LEN1{1'b1}}, ResSgn, ResExp[`NE1-1:0], ResFrac[`NF-1:`NF-`NF1]}; + + end else if (`FPSIZES == 3) begin + always_comb + case (OutFmt) + `FMT: begin + // IEEE sends a payload while Riscv says to send a canonical quiet NaN + if(`IEEE754) begin + NaNRes = {1'b0, {`NE+1{1'b1}}, XManE[`NF-2:0]}; + end else begin + NaNRes = {1'b0, {`NE+1{1'b1}}, {`NF-1{1'b0}}}; + end + // determine the infinity result + // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - otherwise: output infinity with the correct sign + // - kill the infinity singal if the input isn't fp + InfRes = (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {ResSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {ResSgn, {`NE{1'b1}}, {`NF{1'b0}}}; + + // result for when the result is killed i.e. underflowes + // - output a rounded 0 with the correct sign + UfRes = {ResSgn, (`FLEN-2)'(0), Plus1&FrmE[1]}; + + // format the result - NaN box single precision (put 1's in the unused msbs) + Res = {ResSgn, ResExp, ResFrac}; + end + `FMT1: begin + // IEEE sends a payload while Riscv says to send a canonical quiet NaN + if(`IEEE754) begin + NaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, XManE[`NF-2:`NF-`NF1]}; + end else begin + NaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1+1{1'b1}}, {`NF1-1{1'b0}}}; + end + // determine the infinity result + // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - otherwise: output infinity with the correct sign + // - kill the infinity singal if the input isn't fp + InfRes = (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1{1'b1}}, (`NF1)'(0)}; + + // result for when the result is killed i.e. underflowes + // - output a rounded 0 with the correct sign + UfRes = {{`FLEN-`LEN1{1'b1}}, ResSgn, (`LEN1-2)'(0), Plus1&FrmE[1]}; + + // format the result - NaN box single precision (put 1's in the unused msbs) + Res = {{`FLEN-`LEN1{1'b1}}, ResSgn, ResExp[`NE1-1:0], ResFrac[`NF-1:`NF-`NF1]}; + end + `FMT2: begin + // IEEE sends a payload while Riscv says to send a canonical quiet NaN + if(`IEEE754) begin + NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2+1{1'b1}}, XManE[`NF-2:`NF-`NF2]}; + end else begin + NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2+1{1'b1}}, {`NF2-1{1'b0}}}; + end + // determine the infinity result + // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - otherwise: output infinity with the correct sign + // - kill the infinity singal if the input isn't fp + InfRes = (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {{`FLEN-`LEN2{1'b1}}, ResSgn, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : {{`FLEN-`LEN2{1'b1}}, ResSgn, {`NE2{1'b1}}, (`NF2)'(0)}; + + // result for when the result is killed i.e. underflowes + // - output a rounded 0 with the correct sign + UfRes = {{`FLEN-`LEN2{1'b1}}, ResSgn, (`LEN2-2)'(0), Plus1&FrmE[1]}; + + // format the result - NaN box single precision (put 1's in the unused msbs) + Res = {{`FLEN-`LEN2{1'b1}}, ResSgn, ResExp[`NE2-1:0], ResFrac[`NF-1:`NF-`NF2]}; + end + default: begin + NaNRes = 1'bx; + InfRes = 1'bx; + UfRes = 1'bx; + Res = 1'bx; + end + endcase + end else if (`FPSIZES == 4) begin + always_comb + case (OutFmt) + 2'h3: begin + // IEEE sends a payload while Riscv says to send a canonical quiet NaN + if(`IEEE754) begin + NaNRes = {1'b0, {`Q_NE+1{1'b1}}, XManE[`Q_NF-2:0]}; + end else begin + NaNRes = {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}}; + end + // determine the infinity result + // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - otherwise: output infinity with the correct sign + // - kill the infinity singal if the input isn't fp + InfRes = (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {ResSgn, {`Q_NE-1{1'b1}}, 1'b0, {`Q_NF{1'b1}}} : {ResSgn, {`Q_NE{1'b1}}, {`Q_NF{1'b0}}}; + + // result for when the result is killed i.e. underflowes + // - output a rounded 0 with the correct sign + UfRes = {ResSgn, (`Q_LEN-2)'(0), Plus1&FrmE[1]}; + + // format the result - NaN box single precision (put 1's in the unused msbs) + Res = {ResSgn, ResExp, ResFrac}; + end + 2'h1: begin + // IEEE sends a payload while Riscv says to send a canonical quiet NaN + if(`IEEE754) begin + NaNRes = {{`Q_LEN-`D_LEN{1'b1}}, 1'b0, {`D_NE+1{1'b1}}, XManE[`Q_NF-2:`Q_NF-`D_NF]}; + end else begin + NaNRes = {{`Q_LEN-`D_LEN{1'b1}}, 1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}}; + end + // determine the infinity result + // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - otherwise: output infinity with the correct sign + // - kill the infinity singal if the input isn't fp + InfRes = (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {{`Q_LEN-`D_LEN{1'b1}}, ResSgn, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : {{`Q_LEN-`D_LEN{1'b1}}, ResSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; + + // result for when the result is killed i.e. underflowes + // - output a rounded 0 with the correct sign + UfRes = {{`Q_LEN-`D_LEN{1'b1}}, ResSgn, (`D_LEN-2)'(0), Plus1&FrmE[1]}; + + // format the result - NaN box single precision (put 1's in the unused msbs) + Res = {{`Q_LEN-`D_LEN{1'b1}}, ResSgn, ResExp[`D_NE-1:0], ResFrac[`Q_NF-1:`Q_NF-`D_NF]}; + end + 2'h0: begin + // IEEE sends a payload while Riscv says to send a canonical quiet NaN + if(`IEEE754) begin + NaNRes = {{`Q_LEN-`S_LEN{1'b1}}, 1'b0, {`S_NE+1{1'b1}}, XManE[`Q_NF-2:`Q_NF-`S_NF]}; + end else begin + NaNRes = {{`Q_LEN-`S_LEN{1'b1}}, 1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}}; + end + // determine the infinity result + // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - otherwise: output infinity with the correct sign + // - kill the infinity singal if the input isn't fp + InfRes = (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {{`Q_LEN-`S_LEN{1'b1}}, ResSgn, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : {{`Q_LEN-`S_LEN{1'b1}}, ResSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; + + // result for when the result is killed i.e. underflowes + // - output a rounded 0 with the correct sign + UfRes = {{`Q_LEN-`S_LEN{1'b1}}, ResSgn, (`S_LEN-2)'(0), Plus1&FrmE[1]}; + + // format the result - NaN box single precision (put 1's in the unused msbs) + Res = {{`Q_LEN-`S_LEN{1'b1}}, ResSgn, ResExp[`S_NE-1:0], ResFrac[`Q_NF-1:`Q_NF-`S_NF]}; + end + 2'h2: begin + // IEEE sends a payload while Riscv says to send a canonical quiet NaN + if(`IEEE754) begin + NaNRes = {{`Q_LEN-`H_LEN{1'b1}}, 1'b0, {`H_NE+1{1'b1}}, XManE[`Q_NF-2:`Q_NF-`H_NF]}; + end else begin + NaNRes = {{`Q_LEN-`H_LEN{1'b1}}, 1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}}; + end + // determine the infinity result + // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - otherwise: output infinity with the correct sign + // - kill the infinity singal if the input isn't fp + InfRes = (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; + + // result for when the result is killed i.e. underflowes + // - output a rounded 0 with the correct sign + UfRes = {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, (`H_LEN-2)'(0), Plus1&FrmE[1]}; + + // format the result - NaN box single precision (put 1's in the unused msbs) + Res = {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, ResExp[`H_NE-1:0], ResFrac[`Q_NF-1:`Q_NF-`H_NF]}; + end + endcase end - // assign InfRes = FOpCtrlE[1:0] == `FMT ? {ResSgn, {`NE{1'b1}}, (`NF)'(0)} : {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1{1'b1}}, (`NF1)'(0)}; -// output one less then the maximum value if rounding down (RZ RU RD) -// if infinitiy output infinity - assign InfRes = FOpCtrlE[1:0] == `FMT ? ~XInfE&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {ResSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : - {ResSgn, {`NE{1'b1}}, {`NF{1'b0}}} : - ~XInfE&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : - {{`FLEN-`LEN1{1'b1}}, ResSgn, {`NE1{1'b1}}, (`NF1)'(0)}; -// if RU/RD then round the underflowed result if needed -// integer zero's exponent is not calculated corresctly so go through underflow result - assign UfRes = OutFmt ? {ResSgn, (`FLEN-2)'(0), Plus1&FrmE[1]} : {{`FLEN-`LEN1{1'b1}}, ResSgn, (`LEN1-2)'(0), Plus1&FrmE[1]}; - assign Res = OutFmt ? {ResSgn, ResExp, ResFrac} : {{`FLEN-`LEN1{1'b1}}, ResSgn, ResExp[`NE1-1:0], ResFrac[`NF-1:`NF-`NF1]}; + + + // choose the floating point result + // - if the input is NaN (and using the NaN input) output the NaN result + // - if the input is infinity or the output overflows + // - kill the InfE signal if the input isn't a floating point value + // - if killing the result output the underflow result + // - otherwise output the normal result assign CvtResE = XNaNE&~IntToFp ? NaNRes : - (XInfE|Overflow)&~IntToFp ? InfRes : + (XInfE&~IntToFp)|Overflow ? InfRes : KillRes ? UfRes : Res; // *** probably can optimize the negation - // NaNs sould ouput the same as a positive infinity - // a 32bit unsigend result should be sign extended (as if it is not a unsigned number) + // select the overflow integer result + // - negitive infinity and out of range negitive input + // | int | long | + // signed | -2^31 | -2^63 | + // unsigned | 0 | 0 | + // + // - positive infinity and out of range negitive input and NaNs + // | int | long | + // signed | 2^31-1 | 2^63-1 | + // unsigned | 2^32-1 | 2^64-1 | + // + // other: 32 bit unsinged result should be sign extended as if it were a signed number assign OfIntRes = Signed ? XSgnE&~XNaNE ? Int64 ? {1'b1, {`XLEN-1{1'b0}}} : {{`XLEN-32{1'b1}}, 1'b1, {31{1'b0}}} : // signed negitive - Int64 ? {1'b0, {`XLEN-1{1'b1}}} : {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}} : // signed positive - XSgnE&~XNaNE ? {`XLEN{1'b0}} : // unsigned negitive - {`XLEN{1'b1}};// unsigned positive + Int64 ? {1'b0, {`XLEN-1{1'b1}}} : {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}} : // signed positive + XSgnE&~XNaNE ? {`XLEN{1'b0}} : // unsigned negitive + {`XLEN{1'b1}};// unsigned positive - - assign NegRes = XSgnE ? -({2'b0, Shifted[`LGLEN+`NF:`LGLEN+`NF+1-`XLEN]}+{{`XLEN+1{1'b0}},Plus1}) : {2'b0, Shifted[`LGLEN+`NF:`LGLEN+`NF+1-`XLEN]}+{{`XLEN+1{1'b0}},Plus1}; + // round and negate the positive result if needed + assign NegRes = XSgnE ? -({2'b0, Shifted[`LGLEN+`NF:`LGLEN+`NF+1-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`LGLEN+`NF:`LGLEN+`NF+1-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}; + // select the integer output + // - if the input is invalid (out of bounds NaN or Inf) then output overflow result + // - if the input underflows + // - if rounding and signed opperation and negitive input, output -1 + // - otherwise output a rounded 0 + // - otherwise output the normal result (trmined and sign extended if nessisary) assign CvtIntResE = Invalid ? OfIntRes : - CalcExp[`NE] ? XSgnE&Signed&Plus1 ? {{`XLEN{1'b1}}} : {{`XLEN-1{1'b0}}, Plus1} : //CalcExp has to come after invalid ***swap to actual mux at some point?? - Int64 ? NegRes[`XLEN-1:0] : {{`XLEN-32{NegRes[31]}}, NegRes[31:0]}; + CalcExp[`NE] ? XSgnE&Signed&Plus1 ? {{`XLEN{1'b1}}} : {{`XLEN-1{1'b0}}, Plus1} : //CalcExp has to come after invalid ***swap to actual mux at some point?? + Int64 ? NegRes[`XLEN-1:0] : {{`XLEN-32{NegRes[31]}}, NegRes[31:0]}; endmodule \ No newline at end of file diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 0870acad4..3e90aeaf4 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -545,15 +545,15 @@ module testbenchfp; Fmt = {Fmt, 2'b10}; end if (`XLEN == 64) begin // if 64-bit integers are supported - Tests = {Tests, f16rv64cvtint, f16rv32cvtint}; - // add the op-codes for these tests to the op-code list - OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; - WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; - // add what unit is used and the fmt to their lists (one for each test) - for(int i = 0; i<20; i++) begin - Unit = {Unit, `CVTINTUNIT}; - Fmt = {Fmt, 2'b10}; - end + Tests = {Tests, f16rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b10}; + end end end if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested @@ -1187,9 +1187,9 @@ end // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... - else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&XSgn&(Res === (`FLEN)'(0))) | - (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&OpCtrlVal[1]&(Res === {1'b0, {`FLEN-1{1'b1}}})) | - (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&~OpCtrlVal[1]&(Res === {{`FLEN{1'b0}}, 1'b0, {31{1'b1}}})) | + else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&XSgn&(Res[`XLEN-1:0] === (`XLEN)'(0))) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~XSgn|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | (Res === Ans | NaNGood | NaNGood === 1'bx)) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin errors += 1; $display("There is an error in %s", Tests[TestNum]); diff --git a/pipelined/testbench/tests-fp.vh b/pipelined/testbench/tests-fp.vh index d872da717..15abb6525 100644 --- a/pipelined/testbench/tests-fp.vh +++ b/pipelined/testbench/tests-fp.vh @@ -54,16 +54,6 @@ `define CMPUNIT 4 string f16rv32cvtint[] = '{ - "f16_to_i32_rne.tv", - "f16_to_i32_rz.tv", - "f16_to_i32_ru.tv", - "f16_to_i32_rd.tv", - "f16_to_i32_rnm.tv", - "f16_to_ui32_rne.tv", - "f16_to_ui32_rz.tv", - "f16_to_ui32_ru.tv", - "f16_to_ui32_rd.tv", - "f16_to_ui32_rnm.tv", "ui32_to_f16_rne.tv", "ui32_to_f16_rz.tv", "ui32_to_f16_ru.tv", @@ -73,20 +63,20 @@ string f16rv32cvtint[] = '{ "i32_to_f16_rz.tv", "i32_to_f16_ru.tv", "i32_to_f16_rd.tv", - "i32_to_f16_rnm.tv" + "i32_to_f16_rnm.tv", + "f16_to_ui32_rne.tv", + "f16_to_ui32_rz.tv", + "f16_to_ui32_ru.tv", + "f16_to_ui32_rd.tv", + "f16_to_ui32_rnm.tv", + "f16_to_i32_rne.tv", + "f16_to_i32_rz.tv", + "f16_to_i32_ru.tv", + "f16_to_i32_rd.tv", + "f16_to_i32_rnm.tv" }; string f16rv64cvtint[] = '{ - "f16_to_ui64_rne.tv", - "f16_to_ui64_rz.tv", - "f16_to_ui64_ru.tv", - "f16_to_ui64_rd.tv", - "f16_to_ui64_rnm.tv", - "f16_to_i64_rne.tv", - "f16_to_i64_rz.tv", - "f16_to_i64_ru.tv", - "f16_to_i64_rd.tv", - "f16_to_i64_rnm.tv", "ui64_to_f16_rne.tv", "ui64_to_f16_rz.tv", "ui64_to_f16_ru.tv", @@ -96,7 +86,17 @@ string f16rv64cvtint[] = '{ "i64_to_f16_rz.tv", "i64_to_f16_ru.tv", "i64_to_f16_rd.tv", - "i64_to_f16_rnm.tv" + "i64_to_f16_rnm.tv", + "f16_to_ui64_rne.tv", + "f16_to_ui64_rz.tv", + "f16_to_ui64_ru.tv", + "f16_to_ui64_rd.tv", + "f16_to_ui64_rnm.tv", + "f16_to_i64_rne.tv", + "f16_to_i64_rz.tv", + "f16_to_i64_ru.tv", + "f16_to_i64_rd.tv", + "f16_to_i64_rnm.tv" }; string f32rv32cvtint[] = '{ @@ -307,16 +307,16 @@ string f128f32cvt[] = '{ string f128f64cvt[] = '{ - "f64_to_f128_rne.tv", - "f64_to_f128_rz.tv", - "f64_to_f128_ru.tv", - "f64_to_f128_rd.tv", - "f64_to_f128_rnm.tv", "f128_to_f64_rne.tv", "f128_to_f64_rz.tv", "f128_to_f64_ru.tv", "f128_to_f64_rd.tv", - "f128_to_f64_rnm.tv" + "f128_to_f64_rnm.tv", + "f64_to_f128_rne.tv", + "f64_to_f128_rz.tv", + "f64_to_f128_ru.tv", + "f64_to_f128_rd.tv", + "f64_to_f128_rnm.tv" }; string f16add[] = '{ From e76986b31eb0f4f79c87d3bd1b7abf2e4032060c Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Thu, 26 May 2022 20:51:00 +0000 Subject: [PATCH 17/28] fixed synth scraping, best delay plotting --- synthDC/ppaAnalyze.py | 163 +-- synthDC/ppaData.csv | 2429 ++++++++++++++++++++--------------------- 2 files changed, 1295 insertions(+), 1297 deletions(-) diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index d9435772f..0d8243a94 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -24,60 +24,69 @@ def synthsfromcsv(filename): except: pass allSynths[i] = Synth(*allSynths[i]) -def synthsintocsv(mod=None, width=None): +def synthsintocsv(): ''' writes a CSV with one line for every available synthesis each line contains the module, tech, width, target freq, and resulting metrics ''' - specStr = '' - if mod != None: - specStr = mod - if width != None: - specStr += ('_'+str(width)) - specStr += '*' + + bashCommand = "find . -path '*runs/ppa*rv32e*' -prune" + output = subprocess.check_output(['bash','-c', bashCommand]) + allSynths = output.decode("utf-8").split('\n')[:-1] - bashCommand = "grep 'Critical Path Length' runs/ppa_{}/reports/*qor*".format(specStr) - outputCPL = subprocess.check_output(['bash','-c', bashCommand]) - linesCPL = outputCPL.decode("utf-8").split('\n')[:-1] - - bashCommand = "grep 'Design Area' runs/ppa_{}/reports/*qor*".format(specStr) - outputDA = subprocess.check_output(['bash','-c', bashCommand]) - linesDA = outputDA.decode("utf-8").split('\n')[:-1] - - bashCommand = "grep '100' runs/ppa_{}/reports/*power*".format(specStr) - outputP = subprocess.check_output(['bash','-c', bashCommand]) - linesP = outputP.decode("utf-8").split('\n')[:-1] - - cpl = re.compile('\d{1}\.\d{6}') - f = re.compile('_\d*_MHz') - wm = re.compile('ppa_\w*_\d*_qor') - da = re.compile('\d*\.\d{6}') - p = re.compile('\d+\.\d+[e-]*\d+') - t = re.compile('[a-zA-Z0-9]+nm') + specReg = re.compile('[a-zA-Z0-9]+') + metricReg = re.compile('\d+\.\d+[e]?[-+]?\d*') file = open("ppaData.csv", "w") writer = csv.writer(file) writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (mJ)']) - for i in range(len(linesCPL)): - line = linesCPL[i] - mwm = wm.findall(line)[0][4:-4].split('_') - freq = int(f.findall(line)[0][1:-4]) - delay = float(cpl.findall(line)[0]) - area = float(da.findall(linesDA[i])[0]) - mod = mwm[0] - width = int(mwm[1]) - tech = t.findall(line)[0][:-2] - try: #fix - power = p.findall(linesP[i]) - lpower = float(power[2]) - denergy = float(power[1])*delay - except: - lpower = 0 - denergy = 0 + for oneSynth in allSynths: + module, width, risc, tech, freq = specReg.findall(oneSynth)[2:7] + tech = tech[:-2] + metrics = [] + for phrase in [['Path Length', 'qor'], ['Design Area', 'qor'], ['100', 'power']]: + bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*{}*' + bashCommand = bashCommand.format(*phrase) + try: output = subprocess.check_output(['bash','-c', bashCommand]) + except: print("At least one synth run doesn't have reports, try cleanup() first") + nums = metricReg.findall(str(output)) + nums = [float(m) for m in nums] + metrics += nums + delay = metrics[0] + area = metrics[1] + lpower = metrics[4] + denergy = (metrics[2] + metrics[3])*delay # (switching + internal powers)*delay - writer.writerow([mod, tech, width, freq, delay, area, lpower, denergy]) + writer.writerow([module, tech, width, freq, delay, area, lpower, denergy]) file.close() +def cleanup(): + ''' removes runs that didn't work + ''' + bashCommand = 'grep -r "Error" runs/ppa*/reports/*qor*' + try: + output = subprocess.check_output(['bash','-c', bashCommand]) + allSynths = output.decode("utf-8").split('\n')[:-1] + for run in allSynths: + run = run.split('MHz')[0] + bc = 'rm -r '+ run + '*' + output = subprocess.check_output(['bash','-c', bc]) + except: pass + + bashCommand = "find . -path '*runs/ppa*rv32e*' -prune" + output = subprocess.check_output(['bash','-c', bashCommand]) + allSynths = output.decode("utf-8").split('\n')[:-1] + for oneSynth in allSynths: + for phrase in [['Path Length', 'qor'], ['Design Area', 'qor'], ['100', 'power']]: + bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*{}*' + bashCommand = bashCommand.format(*phrase) + try: output = subprocess.check_output(['bash','-c', bashCommand]) + except: + bc = 'rm -r '+ oneSynth[2:] + try: output = subprocess.check_output(['bash','-c', bc]) + except: pass + print("All cleaned up!") + def getVals(tech, module, var, freq=None): ''' for a specified tech, module, and variable/metric returns a list of values for that metric in ascending width order with the appropriate units @@ -112,7 +121,8 @@ def getVals(tech, module, var, freq=None): m = oneSynth.delay osdict = oneSynth._asdict() met = osdict[var] - metric += [met] + try: metric += [met] + except: pass if ('flop' in module) & (var == 'area'): metric = [m/2 for m in metric] # since two flops in each module @@ -144,9 +154,9 @@ def genLegend(fits, coefs, r2, techcolor): eq += " + " + coefsr[ind] + "*Nlog2(N)" ind += 1 - tech, c = techcolor + tech, c, m = techcolor legend_elements = [lines.Line2D([0], [0], color=c, label=eq), - lines.Line2D([0], [0], color=c, ls='', marker='o', label=tech +' $R^2$='+ str(round(r2, 4)))] + lines.Line2D([0], [0], color=c, ls='', marker=m, label=tech +' $R^2$='+ str(round(r2, 4)))] return legend_elements def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): @@ -167,13 +177,13 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): global techcolors global widths for combo in techcolors: - tech, c = combo + tech, c, m = combo metric, units = getVals(tech, module, var, freq=freq) if len(metric) == 5: xp, pred, leg = regress(widths, metric, combo, fits) fullLeg += leg - ax.scatter(widths, metric, color=c) + ax.scatter(widths, metric, color=c, marker=m) ax.plot(xp, pred, color=c) ax.legend(handles=fullLeg) @@ -183,7 +193,7 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): ax.set_ylabel(str.title(var) + units) if singlePlot: - titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (min delay)" + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best delay)" ax.set_title(module + titleStr) plt.show() @@ -266,17 +276,14 @@ def noOutliers(freqs, delays, areas): f=[] d=[] a=[] - - try: - ind = delays.index(min(delays)) - med = freqs[ind] - for i in range(len(freqs)): - norm = freqs[i]/med - if (norm > 0.25) & (norm<1.75): - f += [freqs[i]] - d += [delays[i]] - a += [areas[i]] - except: pass + ind = delays.index(min(delays)) + med = freqs[ind] + for i in range(len(freqs)): + norm = freqs[i]/med + if (norm > 0.25) & (norm<1.75): + f += [freqs[i]] + d += [delays[i]] + a += [areas[i]] return f, d, a @@ -292,7 +299,7 @@ def freqPlot(tech, mod, width): delaysL[ind] += [oneSynth.delay] areasL[ind] += [oneSynth.area] - f, (ax1, ax2, ax3, ax4, ax5) = plt.subplots(5, 1, sharex=True) + f, (ax1, ax2, ax3, ax4) = plt.subplots(4, 1, sharex=True) for ind in [0,1]: areas = areasL[ind] @@ -300,17 +307,15 @@ def freqPlot(tech, mod, width): freqs = freqsL[ind] if ('flop' in mod): areas = [m/2 for m in areas] # since two flops in each module - freqs, delays, areas = noOutliers(freqs, delays, areas) + freqs, delays, areas = noOutliers(freqs, delays, areas) # comment out to see all syntheses c = 'blue' if ind else 'green' - adprod = adprodpow(areas, delays, 2) - adpow = adprodpow(areas, delays, 3) - adpow2 = adprodpow(areas, delays, 4) + adprod = adprodpow(areas, delays, 1) + adpow = adprodpow(areas, delays, 2) ax1.scatter(freqs, delays, color=c) ax2.scatter(freqs, areas, color=c) ax3.scatter(freqs, adprod, color=c) ax4.scatter(freqs, adpow, color=c) - ax5.scatter(freqs, adpow2, color=c) legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] @@ -341,22 +346,26 @@ def plotPPA(mod, freq=None): overlays data from both techs ''' fig, axs = plt.subplots(2, 2) - oneMetricPlot(mod, 'delay', ax=axs[0,0], fits='clg', freq=freq) + oneMetricPlot(mod, 'delay', ax=axs[0,0], fits='cg', freq=freq) oneMetricPlot(mod, 'area', ax=axs[0,1], fits='s', freq=freq) - oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits='c', freq=freq) + oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits='s', freq=freq) oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits='s', freq=freq) - titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (min delay)" + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best delay)" plt.suptitle(mod + titleStr) plt.show() + +if __name__ == '__main__': -Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy") -techcolors = [['sky90', 'green'], ['tsmc28', 'blue']] -widths = [8, 16, 32, 64, 128] -synthsintocsv() + # set up stuff, global variables + Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy") + techcolors = [['sky90', 'green', 'o'], ['tsmc28', 'blue', '^']] # add another list here for gf32 + widths = [8, 16, 32, 64, 128] -synthsfromcsv('ppaData.csv') # your csv here! + # synthsintocsv() # slow, run only when new synth runs to add to csv + + synthsfromcsv('ppaData.csv') # your csv here! -### examples -# oneMetricPlot('add', 'delay') -#freqPlot('sky90', 'add', 8) -#plotPPA('add') \ No newline at end of file + ### examples + oneMetricPlot('add', 'delay') + freqPlot('sky90', 'comparator', 16) + plotPPA('add') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index 77f3266b1..b5b0435cc 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -1,1221 +1,1210 @@ Module,Tech,Width,Target Freq,Delay,Area,L Power (nW),D energy (mJ) -add,sky90,128,10,7.100851,1867.879976,465.925,0.035575263509999996 -add,sky90,128,1538,0.633294,4623.64009,632.254,0.27231642 -add,sky90,128,2051,0.486762,4951.940095,885.884,0.35630978399999996 -add,sky90,128,2359,0.423881,5520.340104,1.49,0.451433265 -add,sky90,128,2410,0.414767,5600.700103,1.57,0.456658467 -add,sky90,128,2462,0.406101,5721.240105,1.77,0.477980877 -add,sky90,128,2513,0.397913,6085.800112,2.14,0.516093161 -add,sky90,128,2564,0.436395,6456.240111,2.27,0.615753345 -add,sky90,128,2615,0.390136,6662.040117,2.45,0.6261682799999999 -add,sky90,128,2667,0.394304,7494.060127,3.58,0.76692128 -add,sky90,128,2718,0.407908,7287.280117,3.35,0.7693144879999999 -add,sky90,128,2769,0.431383,6941.340124,2.86,0.742841526 -add,sky90,128,3077,0.387515,7712.60013,2.93,0.9029099500000001 -add,sky90,128,3590,0.386891,6860.000114,2.62,0.913836542 -add,sky90,128,5000,0.389771,7007.980119,2.77,1.289752239 -add,tsmc28,128,1000,0.999599,437.850003,2.04,0.0832665967 -add,tsmc28,128,10080,0.116232,1390.284012,6.67,0.274191288 -add,tsmc28,128,3000,0.310001,473.634002,2.2,0.08432027200000002 -add,tsmc28,128,4500,0.205985,498.204002,2.29,0.087543625 -add,tsmc28,128,4500,0.205985,498.204002,2.29,0.087543625 -add,tsmc28,128,5000,0.197577,488.502002,2.23,0.092070882 -add,tsmc28,128,5040,0.197577,488.502002,2.23,0.09286119 -add,tsmc28,128,6720,0.148758,707.742004,2.94,0.1338822 -add,tsmc28,128,6900,0.144862,733.320004,3.01,0.135590832 -add,tsmc28,128,7350,0.136053,766.962005,3.21,0.142991703 -add,tsmc28,128,7500,0.133327,769.230005,3.23,0.145726411 -add,tsmc28,128,7650,0.130714,800.856007,3.42,0.148621818 -add,tsmc28,128,7728,0.129394,854.910008,3.69,0.153590678 -add,tsmc28,128,7800,0.128157,844.326007,3.65,0.155710755 -add,tsmc28,128,7896,0.12664,894.096008,3.95,0.16260576000000002 -add,tsmc28,128,8232,0.121475,945.504008,4.24,0.1686073 -add,tsmc28,128,8400,0.119042,1050.084009,4.83,0.18808636 -add,tsmc28,128,8568,0.116709,1118.376008,5.15,0.199689099 -add,tsmc28,128,8904,0.112309,1220.184006,5.77,0.210916302 -add,tsmc28,128,9072,0.114839,1455.55201,7.03,0.247248367 -add,tsmc28,128,9408,0.117481,1300.95001,6.2,0.242833227 -add,sky90,16,10,2.032906,221.479998,55.29,0.00116892095 -add,sky90,16,2609,0.375085,405.720008,52.28,0.028731511 -add,sky90,16,2703,0.363987,405.720008,52.464,0.0289369665 -add,sky90,16,3478,0.287131,443.940009,126.253,0.041921126 -add,sky90,16,3604,0.277242,442.960009,136.766,0.044913204 -add,sky90,16,4000,0.249839,551.74001,302.479,0.059711521 -add,sky90,16,4087,0.243761,503.720009,183.936,0.050946049 -add,sky90,16,4144,0.240621,555.660011,274.571,0.056064693000000006 -add,sky90,16,4174,0.239287,549.780011,304.811,0.060061037 -add,sky90,16,4235,0.235896,600.740011,361.949,0.068881632 -add,sky90,16,4261,0.234402,607.60001,368.742,0.06680457 -add,sky90,16,4325,0.231082,624.260011,374.694,0.07048001 -add,sky90,16,4348,0.22992,610.540011,364.173,0.06575712 -add,sky90,16,4415,0.22649,827.120015,595.953,0.09354037 -add,sky90,16,4435,0.22545,666.400011,419.709,0.0789075 -add,sky90,16,4505,0.221872,731.080013,463.35,0.084533232 -add,sky90,16,4522,0.222724,820.260016,626.379,0.090871392 -add,sky90,16,4595,0.221986,817.320014,742.91,0.09190220399999999 -add,sky90,16,4609,0.221986,815.360013,735.998,0.091680218 -add,sky90,16,4685,0.227412,924.140018,742.859,0.109612584 -add,sky90,16,4696,0.227412,866.320016,645.684,0.10392728400000001 -add,sky90,16,4775,0.224325,926.100016,875.917,0.1139571 -add,sky90,16,4865,0.222829,915.320019,765.596,0.105620946 -add,sky90,16,4955,0.220767,802.620015,561.649,0.097799781 -add,sky90,16,5000,0.228259,924.140017,641.631,0.118466421 -add,sky90,16,5135,0.222202,789.880013,544.462,0.095991264 -add,sky90,16,5217,0.22222,824.180016,601.276,0.10177676000000001 -add,sky90,16,5406,0.22338,993.720015,916.992,0.14139954 -add,sky90,16,6000,0.225754,1120.140018,1.01,0.166832206 -add,sky90,16,6087,0.226225,857.500013,678.287,0.14161685000000002 -add,sky90,16,6307,0.225596,1023.12002,1.01,0.162203524 -add,tsmc28,16,1000,0.459597,32.886,116.238,0.004779808799999999 -add,tsmc28,16,11276,0.088457,65.016001,305.664,0.012914721999999998 -add,tsmc28,16,13885,0.072003,111.762,603.843,0.020808866999999998 -add,tsmc28,16,15394,0.068684,178.794,992.074,0.032075427999999996 -add,tsmc28,16,15696,0.065845,210.420001,1.22,0.036675665 -add,tsmc28,16,16300,0.067336,189.63,1.05,0.035418736 -add,tsmc28,16,21130,0.069059,167.832002,946.006,0.042333167 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+flopenr,sky90,32,4707,0.208408,2050.160023,905.261,1.8560816479999998 +mult,sky90,8,1818,0.581954,2672.460046,2200.0,1.6195779819999998 +csa,sky90,64,14693,0.067531,1317.120026,539.796,0.24263888299999997 +flopr,sky90,128,12345,0.177282,5403.720033,2390.0,12.250540763999998 +flopr,sky90,8,12345,0.11919,400.820003,214.285,0.688608306 +mult,sky90,8,1673,0.611485,2094.260033,1390.0,1.0994500299999999 +add,tsmc28,16,35000,0.067289,190.764001,1060.0,0.107124088 +csa,sky90,16,15652,0.062613,407.680008,235.173,0.09629879400000001 +alu,sky90,64,2146,0.465831,11271.960215,4250.0,2.0906495279999997 +priorityencoder,sky90,32,7203,0.111067,293.020006,53.82,0.0121285164 +shiftleft,sky90,8,5000,0.198975,154.840003,31.052,0.0137491725 +flopenr,sky90,8,6663,0.152384,635.040013,414.486,0.664927584 +comparator,sky90,16,10,0.576329,252.840005,31.402,0.0001368781375 +add,tsmc28,64,6902,0.144657,298.242001,1280.0,0.09069993900000001 +priorityonehot,sky90,8,22000,0.054084,157.780003,56.585,0.019383705600000002 +mult,sky90,128,607,1.707473,305974.624156,138000.0,291.971053108 +mult,sky90,32,907,1.102529,29124.620481,20800.0,25.612851199000005 +floprasync,sky90,32,19596,0.071444,1446.480028,643.984,2.155036816 +flopenr,sky90,128,10000,0.229286,8959.160147,4960.0,19.608768006 +add,tsmc28,16,1000,0.459597,32.886,116.238,0.005354305049999999 +decoder,sky90,64,18920,0.069176,905.520014,1070.0,0.15114956000000002 +comparator,sky90,64,4909,0.213022,2891.980026,3400.0,0.6002959959999999 +floprasync,sky90,64,15957,0.071444,2892.960056,1290.0,3.511043936 +comparator,sky90,8,9455,0.106411,345.94,438.668,0.06927356100000001 +add,sky90,128,2051,0.486762,4951.940095,885.884,0.68390061 +mult,sky90,32,6000,1.084816,33519.920555,29100.0,195.28315224 +mult,sky90,64,571,1.751186,58587.340388,11000.0,27.973445163999997 +flop,sky90,16,15000,0.070789,533.119995,259.258,0.8058053448 +priorityencoder,sky90,16,7663,0.104403,159.740003,39.177,0.0079241877 +flop,sky90,32,8476,0.070789,1066.23999,518.516,0.910629696 +add,sky90,64,10,8.474034,927.079988,230.083,0.023015476344 +decoder,sky90,16,24035,0.041561,176.400002,223.236,0.019034938 +alu,sky90,64,1752,0.570589,8920.940172,1800.0,1.428184267 +priorityonehot,sky90,8,25000,0.054084,158.760003,59.967,0.022390775999999998 +priorityencoder,sky90,32,9904,0.111067,293.020006,53.82,0.016671156700000002 +priorityencoder,sky90,8,10000,0.104625,85.260002,26.481,0.007428375 +decoder,sky90,64,10511,0.094204,302.820005,116.69,0.024681448 +add,sky90,16,5000,0.228259,924.140017,641.631,0.18762889800000002 +shiftleft,sky90,8,20000,0.100914,757.540012,1260.0,0.250468548 +add,tsmc28,32,6157,0.144527,110.628001,521.245,0.028515177099999997 +alu,sky90,128,2100,0.517687,28095.620502,14300.0,7.387911177 +decoder,sky90,32,9019,0.104922,155.820003,44.605,0.012359811600000001 +flop,sky90,64,13561,0.070789,2132.47998,1040.0,2.9136752400000003 +flopenr,sky90,16,5496,0.167894,1133.860026,585.835,0.882199023 +floprasync,sky90,32,13437,0.071444,1446.480028,643.984,1.4777476959999998 +csa,sky90,128,16291,0.060643,4264.960083,3250.0,1.339725156 +add,tsmc28,128,7500,0.133327,769.230005,3230.0,0.236922079 +priorityonehot,sky90,8,12000,0.076956,63.700001,16.155,0.0033321947999999995 +add,tsmc28,32,7697,0.12908,133.308001,591.302,0.04040204 +priorityonehot,sky90,8,7500,0.132247,56.840001,8.114,0.00225481135 +add,tsmc28,8,16300,0.061319,32.256,178.524,0.009185586199999998 +decoder,sky90,8,24268,0.040971,42.140001,19.257,0.0023886093000000004 +alu,sky90,128,2722,0.513268,27566.420501,13200.0,8.80767888 +priorityencoder,sky90,128,7032,0.113763,1058.400021,117.974,0.037996841999999996 +flop,sky90,8,15000,0.070789,266.559998,129.629,0.4029734614 +flopenr,sky90,128,20000,0.210945,8479.94003,3830.0,34.87173984 +priorityonehot,sky90,16,11556,0.090809,382.200008,391.295,0.039774342 +shiftleft,sky90,32,5000,0.199946,2419.620024,2110.0,0.5004648380000001 +priorityencoder,sky90,64,7500,0.112447,546.840011,77.149,0.0218596968 +priorityonehot,sky90,8,15000,0.065937,73.500001,15.316,0.004219968 +csa,sky90,64,15013,0.062613,1630.720032,893.318,0.364157208 +shiftleft,sky90,64,4174,0.239544,5090.120088,4170.0,0.9806931359999999 +flopr,sky90,128,13975,0.175571,5639.900023,2930.0,15.638284541 +flopenr,sky90,32,5187,0.205496,2113.860023,972.706,1.9731725920000003 +mult,sky90,128,573,1.745187,296812.604204,108000.0,244.64380403400003 +priorityonehot,sky90,128,4222,0.263015,2585.240036,1320.0,0.217513405 +flop,sky90,64,15257,0.070789,2132.47998,1040.0,3.2780262230000003 From a025014650e5f863888e0ce2de4c6497739de18c Mon Sep 17 00:00:00 2001 From: cturek Date: Thu, 26 May 2022 22:20:43 +0000 Subject: [PATCH 18/28] Implemented on-the-fly conversion for unsigned numbers --- pipelined/srt/srt.sv | 45 +++++++++++++++++++++++++++++++++----- pipelined/srt/testbench.sv | 4 ++-- 2 files changed, 41 insertions(+), 8 deletions(-) diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index c5e837180..5f196c7a1 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -85,14 +85,14 @@ module srt #(parameter Nf=52) ( // Partial Product Generation csa csa(WS, WC, Dsel, qp, WSA, WCA); + + otfc2 otfc2(clk, Start, qp, qz, qm, QuotOTFC); expcalc expcalc(.XExp, .YExp, .calcExp); signcalc signcalc(.XSign, .YSign, .calcSign); srtpostproc postproc(rp, rm, Quot); - - otfc otfc(qp, qz, qm, Quot, QuotOTFC); endmodule module srtpostproc #(parameter N=52) ( @@ -216,13 +216,46 @@ endmodule // otfc // ////////// -module otfc #(parameter N=52) ( +module otfc2 #(parameter N=52) ( + input logic clk, + input logic Start, input logic qp, qz, qm, - input logic [N-1:0] Quot, - output logic [N-1:0] QuotOTFC + output logic [N-1:0] r ); - assign QuotOTFC = Quot; + // The on-the-fly converter transfers the quotient + // bits to the quotient as they come. + // + // This code follows the psuedocode presented in the + // floating point chapter of the book. Right now, + // it is written for Radix-2 division. + // + // QM is Q-1. It allows us to write negative bits + // without using a costly CPA. + logic [N+2:0] Q, QM, QNext, QMNext; + // QR and QMR are the shifted versions of Q and QM. + // They are treated as [N-1:r] size signals, and + // discard the r most significant bits of Q and QM. + logic [N+1:0] QR, QMR; + + flopr #(N+3) Qreg(clk, Start, QNext, Q); + flopr #(N+3) QMreg(clk, Start, QMNext, QM); + + always_comb begin + QR = Q[N+1:0]; + QMR = QM[N+1:0]; // Shift Q and QM + if (qp) begin + QNext = {QR, 1'b1}; + QMNext = {QR, 1'b0}; + end else if (qz) begin + QNext = {QR, 1'b0}; + QMNext = {QMR, 1'b1}; + end else begin // If qp and qz are not true, then qm is + QNext = {QMR, 1'b1}; + QMNext = {QMR, 1'b0}; + end + end + assign r = Q[54] ? Q[53:2] : Q[52:1]; endmodule diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 022fa845f..108b2244b 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -121,8 +121,8 @@ module testbench; begin errors = errors+1; $display("OTFC is %h, should be %h\n", rOTFC, r); - $display("failed/n"); - $stop; + $display("failed\n"); + // $stop; end if (afrac === 52'hxxxxxxxxxxxxx) begin From b765a379e3de4752d5b393d97fd3f308699ffc30 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Thu, 26 May 2022 22:24:39 +0000 Subject: [PATCH 19/28] added square delay area plot --- synthDC/ppaAnalyze.py | 45 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index 0d8243a94..d7f161802 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -7,6 +7,7 @@ import csv import re import matplotlib.pyplot as plt import matplotlib.lines as lines +import matplotlib.axes as axes import numpy as np from collections import namedtuple @@ -330,6 +331,43 @@ def freqPlot(tech, mod, width): ax1.set_title(mod + '_' + str(width)) plt.show() +def squareAreaDelay(tech, mod, width): + ''' plots delay, area, area*delay, and area*delay^2 for syntheses with specified tech, module, width + ''' + global allSynths + freqsL, delaysL, areasL = ([[], []] for i in range(3)) + for oneSynth in allSynths: + if (mod == oneSynth.module) & (width == oneSynth.width) & (tech == oneSynth.tech): + ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period + freqsL[ind] += [oneSynth.freq] + delaysL[ind] += [oneSynth.delay] + areasL[ind] += [oneSynth.area] + + fig = plt.figure() + ax = fig.add_subplot(111) + + for ind in [0,1]: + areas = areasL[ind] + delays = delaysL[ind] + freqs = freqsL[ind] + + if ('flop' in mod): areas = [m/2 for m in areas] # since two flops in each module + freqs, delays, areas = noOutliers(freqs, delays, areas) # comment out to see all syntheses + + c = 'blue' if ind else 'green' + plt.scatter(delays, areas, color=c) + + legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), + lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] + + plt.legend(handles=legend_elements) + + plt.xlabel("Delay Achieved (ns)") + plt.ylabel('Area (sq microns)') + plt.title(mod + '_' + str(width)) + ax.set_aspect(1./ax.get_data_ratio()) + plt.show() + def adprodpow(areas, delays, pow): ''' for each value in [areas] returns area*delay^pow helper function for freqPlot''' @@ -366,6 +404,7 @@ if __name__ == '__main__': synthsfromcsv('ppaData.csv') # your csv here! ### examples - oneMetricPlot('add', 'delay') - freqPlot('sky90', 'comparator', 16) - plotPPA('add') \ No newline at end of file + # oneMetricPlot('add', 'delay') + # freqPlot('sky90', 'comparator', 16) + # plotPPA('add') + squareAreaDelay('sky90', 'comparator', 16) \ No newline at end of file From f7a3855af1c50383bbbc803a66e7f5162df3494d Mon Sep 17 00:00:00 2001 From: cturek Date: Thu, 26 May 2022 22:35:17 +0000 Subject: [PATCH 20/28] fixed sizing issues in expcalc --- pipelined/srt/srt.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index 5f196c7a1..835b1d1b6 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -319,7 +319,7 @@ module expcalc( output logic [`NE-1:0] calcExp ); - assign calcExp = XExp - YExp + `BIAS; + assign calcExp = XExp - YExp + 11'b01111111111; endmodule From 547537d1d3782a147685ab93772b30770da1b336 Mon Sep 17 00:00:00 2001 From: DTowersM Date: Thu, 26 May 2022 23:36:38 +0000 Subject: [PATCH 21/28] embench addition: added options to create .elf, .objdump, .memfile, .addr and .lab files from the executible in the embench build directory --- benchmarks/embench/Makefile | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 3e40a68ab..28b012cd9 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -7,9 +7,14 @@ allClean: clean all build: ../../addins/embench-iot/build_all.py --builddir=bd_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-nostartfiles" - ../../addins/embench-iot/build_all.py --builddir=bd_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib" --cflags="-nostdlib" --dummy-libs="libgcc libm libc crt0" + find ../../addins/embench-iot/bd_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done + ../../addins/embench-iot/build_all.py --builddir=bd_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles" --cflags="-msave-restore" --dummy-libs="libgcc libm libc crt0" -sim: size speed +sim: modelSimBuild size speed + +modelSimBuild: objdump + find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done + find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done size: ../../addins/embench-iot/benchmark_size.py --builddir=bd_size @@ -18,10 +23,7 @@ speed: ../../addins/embench-iot/benchmark_speed.py --builddir=bd_speed --target-module run_wally --cpu-mhz=50 objdump: - riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/aha-mont64/aha-mont64 > ../../addins/embench-iot/bd_speed/src/aha-mont64/aha-mont64.objdump - riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/cubic/cubic > ../../addins/embench-iot/bd_speed/src/cubic/cubic.objdump - riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/md5sum/md5sum > ../../addins/embench-iot/bd_speed/src/md5sum/md5sum.objdump - riscv64-unknown-elf-objdump -S ../../addins/embench-iot/bd_speed/src/statemate/statemate > ../../addins/embench-iot/bd_speed/src/statemate/statemate.objdump + find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-objdump -S "$$f" > "$$f.objdump"; done clean: rm -rf ../../addins/embench-iot/bd_speed/ From efb972c6d30c9037184f0902bf0437cc7fe08857 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Fri, 27 May 2022 08:23:46 -0700 Subject: [PATCH 22/28] Removed guard bit from fma rounding --- pipelined/src/fpu/fma.sv | 138 +++++++++++++-------------------------- 1 file changed, 46 insertions(+), 92 deletions(-) diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 97735c5f7..30b352f0c 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -465,7 +465,7 @@ module fma2( logic ResultSgn, ResultSgnTmp; // Result sign logic [`NE+1:0] SumExp; // exponent of the normalized sum logic [`NE+1:0] FullResultExp; // ResultExp with bits to determine sign and overflow - logic [`NF+2:0] NormSum; // normalized sum + logic [`NF+1:0] NormSum; // normalized sum logic NormSumSticky; // sticky bit calulated from the normalized sum logic SumZero; // is the sum zero logic ResultDenorm; // is the result denormalized @@ -582,7 +582,7 @@ module normalize( input logic KillProdM, // is the product set to zero input logic ZOrigDenormM, input logic AddendStickyM, // the sticky bit caclulated from the aligned addend - output logic [`NF+2:0] NormSum, // normalized sum + output logic [`NF+1:0] NormSum, // normalized sum output logic SumZero, // is the sum zero output logic NormSumSticky, UfSticky, // sticky bits output logic [`NE+1:0] SumExp, // exponent of the normalized sum @@ -707,27 +707,27 @@ module normalize( assign LZAPlus2 = SumShifted[3*`NF+8]; // the only possible mantissa for a plus two is all zeroes - a one has to propigate all the way through a sum. so we can leave the bottom statement alone assign CorrSumShifted = LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0]; - assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3]; + assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+4]; // Calculate the sticky bit if (`FPSIZES == 1) begin - assign NormSumSticky = |CorrSumShifted[2*`NF+2:0]; + assign NormSumSticky = |CorrSumShifted[2*`NF+3:0]; end else if (`FPSIZES == 2) begin // 3*NF+5 - NF1 - 3 - assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | - (|CorrSumShifted[3*`NF+2-`NF1:2*`NF+3]&~FmtM); + assign NormSumSticky = (|CorrSumShifted[2*`NF+3:0]) | + (|CorrSumShifted[3*`NF+3-`NF1:2*`NF+4]&~FmtM); end else if (`FPSIZES == 3) begin - assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | - (|CorrSumShifted[3*`NF+2-`NF1:2*`NF+3]&((FmtM==`FMT1)|(FmtM==`FMT2))) | - (|CorrSumShifted[3*`NF+2-`NF2:3*`NF+3-`NF1]&(FmtM==`FMT2)); + assign NormSumSticky = (|CorrSumShifted[2*`NF+3:0]) | + (|CorrSumShifted[3*`NF+3-`NF1:2*`NF+4]&((FmtM==`FMT1)|(FmtM==`FMT2))) | + (|CorrSumShifted[3*`NF+3-`NF2:3*`NF+4-`NF1]&(FmtM==`FMT2)); end else if (`FPSIZES == 4) begin - assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | - (|CorrSumShifted[3*`NF+2-`D_NF:2*`NF+3]&((FmtM==1)|(FmtM==0)|(FmtM==2))) | - (|CorrSumShifted[3*`NF+2-`S_NF:3*`NF+3-`D_NF]&((FmtM==0)|(FmtM==2))) | - (|CorrSumShifted[3*`NF+2-`H_NF:3*`NF+3-`S_NF]&(FmtM==2)); + assign NormSumSticky = (|CorrSumShifted[2*`NF+3:0]) | + (|CorrSumShifted[3*`NF+3-`D_NF:2*`NF+4]&((FmtM==1)|(FmtM==0)|(FmtM==2))) | + (|CorrSumShifted[3*`NF+3-`S_NF:3*`NF+4-`D_NF]&((FmtM==0)|(FmtM==2))) | + (|CorrSumShifted[3*`NF+3-`H_NF:3*`NF+4-`S_NF]&(FmtM==2)); end @@ -745,7 +745,7 @@ module fmaround( input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single input logic [2:0] FrmM, // rounding mode input logic UfSticky, // sticky bit for underlow calculation - input logic [`NF+2:0] NormSum, // normalized sum + input logic [`NF+1:0] NormSum, // normalized sum input logic AddendStickyM, // addend's sticky bit input logic NormSumSticky, // normalized sum's sticky bit input logic ZZeroM, // is Z zero @@ -799,83 +799,53 @@ module fmaround( if (`FPSIZES == 1) begin // determine guard, round, and least significant bit of the result - assign Guard = NormSum[2]; assign Round = NormSum[1]; - assign LSBNormSum = NormSum[3]; + assign LSBNormSum = NormSum[2]; // used to determine underflow flag - assign UfGuard = NormSum[1]; assign UfRound = NormSum[0]; - assign UfLSBNormSum = NormSum[2]; - - // determine sticky - assign Sticky = UfSticky | NormSum[0]; end else if (`FPSIZES == 2) begin // \/-------------NF---------------, - // | NF1 | 3 | | + // | NF1 | 2 | | // '-------NF1------^ // determine guard, round, and least significant bit of the result - assign Guard = FmtM ? NormSum[2] : NormSum[`NF-`NF1+2]; assign Round = FmtM ? NormSum[1] : NormSum[`NF-`NF1+1]; - assign LSBNormSum = FmtM ? NormSum[3] : NormSum[`NF-`NF1+3]; + assign LSBNormSum = FmtM ? NormSum[2] : NormSum[`NF-`NF1+2]; // used to determine underflow flag - assign UfGuard = FmtM ? NormSum[1] : NormSum[`NF-`NF1+1]; assign UfRound = FmtM ? NormSum[0] : NormSum[`NF-`NF1]; - assign UfLSBNormSum = FmtM ? NormSum[2] : NormSum[`NF-`NF1+2]; - // determine sticky - assign Sticky = UfSticky | (FmtM ? NormSum[0] : NormSum[`NF-`NF1]); end else if (`FPSIZES == 3) begin always_comb begin case (FmtM) `FMT: begin // determine guard, round, and least significant bit of the result - Guard = NormSum[2]; Round = NormSum[1]; - LSBNormSum = NormSum[3]; + LSBNormSum = NormSum[2]; // used to determine underflow flag - UfGuard = NormSum[1]; UfRound = NormSum[0]; - UfLSBNormSum = NormSum[2]; - // determine sticky - Sticky = UfSticky | NormSum[0]; end `FMT1: begin // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`NF1+2]; Round = NormSum[`NF-`NF1+1]; - LSBNormSum = NormSum[`NF-`NF1+3]; + LSBNormSum = NormSum[`NF-`NF1+2]; // used to determine underflow flag - UfGuard = NormSum[`NF-`NF1+1]; UfRound = NormSum[`NF-`NF1]; - UfLSBNormSum = NormSum[`NF-`NF1+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`NF1]; end `FMT2: begin // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`NF2+2]; Round = NormSum[`NF-`NF2+1]; - LSBNormSum = NormSum[`NF-`NF2+3]; + LSBNormSum = NormSum[`NF-`NF2+2]; // used to determine underflow flag - UfGuard = NormSum[`NF-`NF2+1]; UfRound = NormSum[`NF-`NF2]; - UfLSBNormSum = NormSum[`NF-`NF2+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`NF2]; end default: begin - Guard = 1'bx; Round = 1'bx; LSBNormSum = 1'bx; - UfGuard = 1'bx; UfRound = 1'bx; - UfLSBNormSum = 1'bx; - Sticky = 1'bx; end endcase end @@ -885,56 +855,40 @@ module fmaround( case (FmtM) 2'h3: begin // determine guard, round, and least significant bit of the result - Guard = NormSum[2]; Round = NormSum[1]; - LSBNormSum = NormSum[3]; + LSBNormSum = NormSum[2]; // used to determine underflow flag - UfGuard = NormSum[1]; UfRound = NormSum[0]; - UfLSBNormSum = NormSum[2]; - // determine sticky - Sticky = UfSticky | NormSum[0]; end 2'h1: begin // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`D_NF+2]; Round = NormSum[`NF-`D_NF+1]; - LSBNormSum = NormSum[`NF-`D_NF+3]; + LSBNormSum = NormSum[`NF-`D_NF+2]; // used to determine underflow flag - UfGuard = NormSum[`NF-`D_NF+1]; UfRound = NormSum[`NF-`D_NF]; - UfLSBNormSum = NormSum[`NF-`D_NF+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`D_NF]; end 2'h0: begin // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`S_NF+2]; Round = NormSum[`NF-`S_NF+1]; - LSBNormSum = NormSum[`NF-`S_NF+3]; + LSBNormSum = NormSum[`NF-`S_NF+2]; // used to determine underflow flag - UfGuard = NormSum[`NF-`S_NF+1]; UfRound = NormSum[`NF-`S_NF]; - UfLSBNormSum = NormSum[`NF-`S_NF+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`S_NF]; end 2'h2: begin // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`H_NF+2]; Round = NormSum[`NF-`H_NF+1]; - LSBNormSum = NormSum[`NF-`H_NF+3]; + LSBNormSum = NormSum[`NF-`H_NF+2]; // used to determine underflow flag - UfGuard = NormSum[`NF-`H_NF+1]; UfRound = NormSum[`NF-`H_NF]; - UfLSBNormSum = NormSum[`NF-`H_NF+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`H_NF]; end endcase end end + // used to determine underflow flag + assign UfLSBNormSum = Round; + // determine sticky + assign Sticky = UfSticky | UfRound; // Deterimine if a small number was supposed to be subtrated @@ -944,28 +898,28 @@ module fmaround( always_comb begin // Determine if you add 1 case (FrmM) - 3'b000: CalcPlus1 = Guard & (Round | ((Sticky)&~(~Round&SubBySmallNum)) | (~Round&~(Sticky)&LSBNormSum&~SubBySmallNum));//round to nearest even + 3'b000: CalcPlus1 = Round & ((Sticky| LSBNormSum)&~SubBySmallNum);//round to nearest even 3'b001: CalcPlus1 = 0;//round to zero - 3'b010: CalcPlus1 = ResultSgnTmp & ~(SubBySmallNum & ~Guard & ~Round);//round down - 3'b011: CalcPlus1 = ~ResultSgnTmp & ~(SubBySmallNum & ~Guard & ~Round);//round up - 3'b100: CalcPlus1 = (Guard & (Round | ((Sticky)&~(~Round&SubBySmallNum)) | (~Round&~(Sticky)&~SubBySmallNum)));//round to nearest max magnitude + 3'b010: CalcPlus1 = ResultSgnTmp & ~(SubBySmallNum & ~Round);//round down + 3'b011: CalcPlus1 = ~ResultSgnTmp & ~(SubBySmallNum & ~Round);//round up + 3'b100: CalcPlus1 = Round & ~SubBySmallNum;//round to nearest max magnitude default: CalcPlus1 = 1'bx; endcase // Determine if you add 1 (for underflow flag) case (FrmM) - 3'b000: UfCalcPlus1 = UfGuard & (UfRound | (UfSticky&UfRound|~UfSubBySmallNum) | (~Sticky&UfLSBNormSum&~UfSubBySmallNum));//round to nearest even + 3'b000: UfCalcPlus1 = UfRound & ((UfSticky| UfLSBNormSum)&~UfSubBySmallNum);//round to nearest even 3'b001: UfCalcPlus1 = 0;//round to zero - 3'b010: UfCalcPlus1 = ResultSgnTmp & ~(UfSubBySmallNum & ~UfGuard & ~UfRound);//round down - 3'b011: UfCalcPlus1 = ~ResultSgnTmp & ~(UfSubBySmallNum & ~UfGuard & ~UfRound);//round up - 3'b100: UfCalcPlus1 = (UfGuard & (UfRound | (UfSticky&~(~UfRound&UfSubBySmallNum)) | (~Sticky&~UfSubBySmallNum)));//round to nearest max magnitude + 3'b010: UfCalcPlus1 = ResultSgnTmp & ~(UfSubBySmallNum & ~UfRound);//round down + 3'b011: UfCalcPlus1 = ~ResultSgnTmp & ~(UfSubBySmallNum & ~UfRound);//round up + 3'b100: UfCalcPlus1 = UfRound & ~UfSubBySmallNum;//round to nearest max magnitude default: UfCalcPlus1 = 1'bx; endcase // Determine if you subtract 1 case (FrmM) 3'b000: CalcMinus1 = 0;//round to nearest even - 3'b001: CalcMinus1 = SubBySmallNum & ~Guard & ~Round;//round to zero - 3'b010: CalcMinus1 = ~ResultSgnTmp & ~Guard & ~Round & SubBySmallNum;//round down - 3'b011: CalcMinus1 = ResultSgnTmp & ~Guard & ~Round & SubBySmallNum;//round up + 3'b001: CalcMinus1 = SubBySmallNum & ~Round;//round to zero + 3'b010: CalcMinus1 = ~ResultSgnTmp & ~Round & SubBySmallNum;//round down + 3'b011: CalcMinus1 = ResultSgnTmp & ~Round & SubBySmallNum;//round up 3'b100: CalcMinus1 = 0;//round to nearest max magnitude default: CalcMinus1 = 1'bx; endcase @@ -973,9 +927,9 @@ module fmaround( end // If an answer is exact don't round - assign Plus1 = CalcPlus1 & (Sticky | Guard | Round); - assign UfPlus1 = UfCalcPlus1 & (Sticky | UfGuard);//UfRound is part of sticky - assign Minus1 = CalcMinus1 & (Sticky | Guard | Round); + assign Plus1 = CalcPlus1 & (Sticky | Round); + assign UfPlus1 = UfCalcPlus1 & (Sticky | UfRound);//UfRound is part of sticky + assign Minus1 = CalcMinus1 & (Sticky | Round); // Compute rounded result if (`FPSIZES == 1) begin @@ -1011,7 +965,7 @@ module fmaround( end - assign NormSumTruncated = NormSum[`NF+2:3]; + assign NormSumTruncated = NormSum[`NF+1:2]; assign {FullResultExp, ResultFrac} = {SumExp, NormSumTruncated} + RoundAdd; assign ResultExp = FullResultExp[`NE-1:0]; @@ -1083,12 +1037,12 @@ module fmaflags( // Set Underflow flag if the number is too small to be represented in normal numbers // - Don't set the underflow flag if the result is exact - assign Underflow = (SumExp[`NE+1] | ((SumExp == 0) & (Round|Guard|Sticky)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); + assign Underflow = (SumExp[`NE+1] | ((SumExp == 0) & (Round|Sticky)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); // exp is negitive result is denorm exp was denorm but rounded to norm and if given an unbounded exponent it would stay denormal - assign UnderflowFlag = (FullResultExp[`NE+1] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Guard|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); + assign UnderflowFlag = (FullResultExp[`NE+1] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); // Set Inexact flag if the result is diffrent from what would be outputed given infinite precision // - Don't set the underflow flag if an underflowed result isn't outputed - assign Inexact = (Sticky|Overflow|Guard|Round|Underflow)&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); + assign Inexact = (Sticky|Overflow|Round|Underflow)&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); // Combine flags // - FMA can't set the Divide by zero flag From b288f812ab282848cbc5c4933e656b825b9299ea Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Fri, 27 May 2022 09:04:02 -0700 Subject: [PATCH 23/28] moved lzc to generic and small optimizations on fcvt --- pipelined/regression/fp.do | 2 +- pipelined/src/fpu/fcvt.sv | 39 +++++++++++++----------------------- pipelined/src/fpu/fma.sv | 14 +------------ pipelined/src/generic/lzc.sv | 13 ++++++++++++ 4 files changed, 29 insertions(+), 39 deletions(-) create mode 100644 pipelined/src/generic/lzc.sv diff --git a/pipelined/regression/fp.do b/pipelined/regression/fp.do index 208118fc6..68c240c8a 100644 --- a/pipelined/regression/fp.do +++ b/pipelined/regression/fp.do @@ -32,7 +32,7 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # $num = the added words after the call -vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv -suppress 2583,7063,8607,2697 +vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/generic/*.sv -suppress 2583,7063,8607,2697 vsim -voptargs=+acc work.testbenchfp -G TEST=$2 diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index 55e6706c5..dfe98a793 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -39,9 +39,10 @@ module fcvt ( logic [`FPSIZES/3:0] OutFmt; // format of the output logic [`XLEN-1:0] PosInt; // the positive integer input + logic [`XLEN-1:0] TrimInt; // integer trimmed to the correct size logic [`LGLEN-1:0] LzcIn; // input to the Leading Zero Counter (priority encoder) logic [`NE:0] CalcExp; // the calculated expoent - logic [$clog2(`LGLEN):0] ShiftAmt; // how much to shift by + logic [$clog2(`LGLEN)-1:0] ShiftAmt; // how much to shift by logic [`LGLEN+`NF:0] ShiftIn; // number to be shifted logic ResDenormUf;// does the result underflow or is denormalized logic ResUf; // does the result underflow @@ -71,6 +72,7 @@ module fcvt ( logic Int64; // is the integer 64 bits? logic IntToFp; // is the opperation an int->fp conversion? logic ToInt; // is the opperation an fp->int conversion? + logic [$clog2(`LGLEN)-1:0] ZeroCnt; // output from the LZC // seperate OpCtrl for code readability @@ -91,18 +93,11 @@ module fcvt ( /////////////////////////////////////////////////////////////////////////// // negation /////////////////////////////////////////////////////////////////////////// - // negate the input if the input is a negitive singed integer - // - remove leading ones if the input is a unsigned 32-bit integer - // - // Negitive input - // 64-bit input : negate the input - // 32-bit input : trim to 32-bits and negate the input - // Positive input - // 64-bit input : do nothing - // 32-bit input : trim to 32-bits + // 1) negate the input if the input is a negitive singed integer + // 2) trim the input to the proper size (kill the 32 most significant zeroes if needed) - assign PosInt = ResSgn ? Int64 ? -ForwardedSrcAE : {{`XLEN-32{1'b0}}, -ForwardedSrcAE[31:0]} : - Int64 ? ForwardedSrcAE : {{`XLEN-32{1'b0}}, ForwardedSrcAE[31:0]}; + assign PosInt = ResSgn ? -ForwardedSrcAE : ForwardedSrcAE; + assign TrimInt = {{`XLEN-32{Int64}}, {32{1'b1}}} & PosInt; /////////////////////////////////////////////////////////////////////////// // lzc @@ -111,16 +106,10 @@ module fcvt ( // choose the input to the leading zero counter i.e. priority encoder // int -> fp : | positive integer | 00000... (if needed) | // fp -> fp : | fraction | 00000... (if needed) | - assign LzcIn = IntToFp ? {PosInt, {`LGLEN-`XLEN{1'b0}}} : // I->F - {XManE[`NF-1:0], {`LGLEN-`NF{1'b0}}}; // F->F + assign LzcIn = IntToFp ? {TrimInt, {`LGLEN-`XLEN{1'b0}}} : + {XManE[`NF-1:0], {`LGLEN-`NF{1'b0}}}; - // lglen is the largest possible value of ZeroCnt (NF or XLEN) hence normcnt must be log2(lglen) bits - logic [$clog2(`LGLEN):0] i, ZeroCnt; - always_comb begin - i = 0; - while (~LzcIn[`LGLEN-1-i] & i <= `LGLEN-1) i = i+1; // search for leading one - ZeroCnt = i; - end + lzc #(`LGLEN) lzc (.num(LzcIn), .ZeroCnt); /////////////////////////////////////////////////////////////////////////// @@ -154,9 +143,9 @@ module fcvt ( // - only shift fp -> fp if the intital value is denormalized // - this is a problem because the input to the lzc was the fraction rather than the mantissa // - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true? - assign ShiftAmt = ToInt ? CalcExp[$clog2(`LGLEN):0]&{$clog2(`LGLEN)+1{~CalcExp[`NE]}} : - ResDenormUf&~IntToFp ? ($clog2(`LGLEN)+1)'(`NF-1)+CalcExp[$clog2(`LGLEN):0] : - (ZeroCnt+1)&{$clog2(`LGLEN)+1{XOrigDenormE|IntToFp}}; + assign ShiftAmt = ToInt ? CalcExp[$clog2(`LGLEN)-1:0]&{$clog2(`LGLEN){~CalcExp[`NE]}} : + ResDenormUf&~IntToFp ? ($clog2(`LGLEN))'(`NF-1)+CalcExp[$clog2(`LGLEN)-1:0] : + (ZeroCnt+1)&{$clog2(`LGLEN){XOrigDenormE|IntToFp}}; // shift // fp -> int: | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp @@ -568,7 +557,7 @@ module fcvt ( // - do so if the result underflows, is zero (the exp doesnt calculate correctly). or the integer input is 0 // - dont set to zero if fp input is zero but not using the fp input // - dont set to zero if int input is zero but not using the int input - assign KillRes = (ResUf|(XZeroE&~IntToFp)|(~|PosInt&IntToFp)); + assign KillRes = (ResUf|(XZeroE&~IntToFp)|(~|TrimInt&IntToFp)); if (`FPSIZES == 1) begin // IEEE sends a payload while Riscv says to send a canonical quiet NaN diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 30b352f0c..179bc264b 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -409,22 +409,10 @@ module loa( //https://ieeexplore.ieee.org/abstract/document/930098 - lzc lzc(.f, .NormCntE); + lzc #(3*`NF+7) lzc (.num(f), .ZeroCnt(NormCntE)); endmodule -module lzc( - input logic [3*`NF+6:0] f, - output logic [$clog2(3*`NF+7)-1:0] NormCntE // normalization shift -); - - logic [$clog2(3*`NF+7)-1:0] i; - always_comb begin - i = 0; - while (~f[3*`NF+6-i] & $unsigned(i) <= $unsigned($clog2(3*`NF+7)'(3)*($clog2(3*`NF+7))'(`NF)+($clog2(3*`NF+7))'(6))) i = i+1; // search for leading one - NormCntE = i; - end -endmodule diff --git a/pipelined/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv new file mode 100644 index 000000000..78ac99e50 --- /dev/null +++ b/pipelined/src/generic/lzc.sv @@ -0,0 +1,13 @@ +//leading zero counter i.e. priority encoder +module lzc #(parameter WIDTH=1) ( + input logic [WIDTH-1:0] num, + output logic [$clog2(WIDTH)-1:0] ZeroCnt +); + + logic [$clog2(WIDTH)-1:0] i; + always_comb begin + i = 0; + while (~num[WIDTH-1-i] & $unsigned(i) <= $unsigned(WIDTH-1)) i = i+1; // search for leading one + ZeroCnt = i; + end +endmodule From 3c63db9554b81a1d35aa46b189412437e4ae56dd Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Fri, 27 May 2022 11:36:04 -0700 Subject: [PATCH 24/28] some optimizations in unpacker --- addins/riscv-arch-test | 2 +- pipelined/src/fpu/fcvt.sv | 10 ++++---- pipelined/src/fpu/fma.sv | 2 +- pipelined/src/fpu/unpack.sv | 36 ++++++++++++++--------------- pipelined/src/generic/lzc.sv | 4 +++- pipelined/testbench/testbench-fp.sv | 6 ++--- 6 files changed, 31 insertions(+), 29 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..ad04e119a 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit ad04e119a5d846a1c11159786ad3382cf5ad3649 diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index dfe98a793..74a2829a0 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -17,9 +17,9 @@ module fcvt ( input logic XSNaNE, // is the input a signaling NaN input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude input logic [`FPSIZES/3:0] FmtE, // the input's precision (11=quad 01=double 00=single 10=half) - output logic [`FLEN-1:0] CvtResE, // the fp to fp conversion's result - output logic [`XLEN-1:0] CvtIntResE, // the fp to fp conversion's result - output logic [4:0] CvtFlgE // the fp to fp conversion's flags + output logic [`FLEN-1:0] CvtResE, // the fp conversion result + output logic [`XLEN-1:0] CvtIntResE, // the int conversion result + output logic [4:0] CvtFlgE // the conversion's flags ); // OpCtrls: @@ -261,7 +261,7 @@ module fcvt ( // - shift left to normilize (-1-ZeroCnt) // - newBias to make the biased exponent // - assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XOrigDenormE|IntToFp} - {{`NE-$clog2(`LGLEN){1'b0}}, (ZeroCnt&{$clog2(`LGLEN)+1{XOrigDenormE|IntToFp}})}; + assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XOrigDenormE|IntToFp} - {{`NE-$clog2(`LGLEN)+1{1'b0}}, (ZeroCnt&{$clog2(`LGLEN){XOrigDenormE|IntToFp}})}; // find if the result is dnormal or underflows // - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) // - can't underflow an integer to Fp conversion @@ -744,7 +744,7 @@ module fcvt ( NaNRes = {{`Q_LEN-`H_LEN{1'b1}}, 1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}}; end // determine the infinity result - // - if the input was infinity or rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign + // - if the input overflows in rounding mode RZ, RU, RD (and not rounding the value) then output the maximum normalized floating point number with the correct sign // - otherwise: output infinity with the correct sign // - kill the infinity singal if the input isn't fp InfRes = (~XInfE|IntToFp)&((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~ResSgn) | (FrmE[1:0]==2'b11&ResSgn)) ? {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 179bc264b..fca4930cd 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -587,7 +587,7 @@ module normalize( /////////////////////////////////////////////////////////////////////////////// // Normalization /////////////////////////////////////////////////////////////////////////////// - //*** insert bias-bias simplification in fcvt.sv/phone pictures/ whiteboard... if still there + //*** insert bias-bias simplification in fcvt.sv/phone pictures // Determine if the sum is zero assign SumZero = ~(|SumM); diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 44ffc2838..06ceff56b 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -96,9 +96,9 @@ module unpack ( // extract the exponent, converting the smaller exponent into the larger precision if nessisary // - if the original precision had a denormal number convert the exponent value 1 - assign XExpE = FmtE ? X[`FLEN-2:`NF] : XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; - assign YExpE = FmtE ? Y[`FLEN-2:`NF] : YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; - assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + assign XExpE = FmtE ? X[`FLEN-2:`NF] : XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]}}, XLen1[`LEN1-3:`NF1]}; + assign YExpE = FmtE ? Y[`FLEN-2:`NF] : YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]}}, YLen1[`LEN1-3:`NF1]}; + assign ZExpE = FmtE ? Z[`FLEN-2:`NF] : ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]}}, ZLen1[`LEN1-3:`NF1]}; // is the input (in it's original format) denormalized assign XOrigDenormE = FmtE ? 0 : ~|XLen1[`LEN1-2:`NF1] & ~XFracZero; @@ -257,9 +257,9 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the larger precision's exponent to use the largest precision's bias - XExpE = XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]&~XExpZero|XExpMaxE}}, XLen1[`LEN1-3:`NF1]}; - YExpE = YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]&~YExpZero|YExpMaxE}}, YLen1[`LEN1-3:`NF1]}; - ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`LEN1-3:`NF1]}; + XExpE = XOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {XLen1[`LEN1-2], {`NE-`NE1{~XLen1[`LEN1-2]}}, XLen1[`LEN1-3:`NF1]}; + YExpE = YOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {YLen1[`LEN1-2], {`NE-`NE1{~YLen1[`LEN1-2]}}, YLen1[`LEN1-3:`NF1]}; + ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE1{1'b1}}, (`NE1-1)'(1)} : {ZLen1[`LEN1-2], {`NE-`NE1{~ZLen1[`LEN1-2]}}, ZLen1[`LEN1-3:`NF1]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen1[`NF1-1:0], (`NF-`NF1)'(0)}; @@ -282,9 +282,9 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the smallest precision's exponent to use the largest precision's bias - XExpE = XOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]&~XExpZero|XExpMaxE}}, XLen2[`LEN2-3:`NF2]}; - YExpE = YOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]&~YExpZero|YExpMaxE}}, YLen2[`LEN2-3:`NF2]}; - ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`LEN2-3:`NF2]}; + XExpE = XOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {XLen2[`LEN2-2], {`NE-`NE2{~XLen2[`LEN2-2]}}, XLen2[`LEN2-3:`NF2]}; + YExpE = YOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {YLen2[`LEN2-2], {`NE-`NE2{~YLen2[`LEN2-2]}}, YLen2[`LEN2-3:`NF2]}; + ZExpE = ZOrigDenormE ? {1'b0, {`NE-`NE2{1'b1}}, (`NE2-1)'(1)} : {ZLen2[`LEN2-2], {`NE-`NE2{~ZLen2[`LEN2-2]}}, ZLen2[`LEN2-3:`NF2]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen2[`NF2-1:0], (`NF-`NF2)'(0)}; @@ -447,9 +447,9 @@ module unpack ( // convert the double precsion exponent into quad precsion - XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {XLen1[`D_LEN-2], {`Q_NE-`D_NE{~XLen1[`D_LEN-2]&~XExpZero|XExpMaxE}}, XLen1[`D_LEN-3:`D_NF]}; - YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {YLen1[`D_LEN-2], {`Q_NE-`D_NE{~YLen1[`D_LEN-2]&~YExpZero|YExpMaxE}}, YLen1[`D_LEN-3:`D_NF]}; - ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen1[`D_LEN-3:`D_NF]}; + XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {XLen1[`D_LEN-2], {`Q_NE-`D_NE{~XLen1[`D_LEN-2]}}, XLen1[`D_LEN-3:`D_NF]}; + YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {YLen1[`D_LEN-2], {`Q_NE-`D_NE{~YLen1[`D_LEN-2]}}, YLen1[`D_LEN-3:`D_NF]}; + ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`D_NE{1'b1}}, (`D_NE-1)'(1)} : {ZLen1[`D_LEN-2], {`Q_NE-`D_NE{~ZLen1[`D_LEN-2]}}, ZLen1[`D_LEN-3:`D_NF]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen1[`D_NF-1:0], (`Q_NF-`D_NF)'(0)}; @@ -471,9 +471,9 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the single precsion exponent into quad precsion - XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {XLen2[`S_LEN-2], {`Q_NE-`S_NE{~XLen2[`S_LEN-2]&~XExpZero|XExpMaxE}}, XLen2[`S_LEN-3:`S_NF]}; - YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {YLen2[`S_LEN-2], {`Q_NE-`S_NE{~YLen2[`S_LEN-2]&~YExpZero|YExpMaxE}}, YLen2[`S_LEN-3:`S_NF]}; - ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {ZLen2[`S_LEN-2], {`Q_NE-`S_NE{~ZLen2[`S_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen2[`S_LEN-3:`S_NF]}; + XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {XLen2[`S_LEN-2], {`Q_NE-`S_NE{~XLen2[`S_LEN-2]}}, XLen2[`S_LEN-3:`S_NF]}; + YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {YLen2[`S_LEN-2], {`Q_NE-`S_NE{~YLen2[`S_LEN-2]}}, YLen2[`S_LEN-3:`S_NF]}; + ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`S_NE{1'b1}}, (`S_NE-1)'(1)} : {ZLen2[`S_LEN-2], {`Q_NE-`S_NE{~ZLen2[`S_LEN-2]}}, ZLen2[`S_LEN-3:`S_NF]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen2[`S_NF-1:0], (`Q_NF-`S_NF)'(0)}; @@ -495,9 +495,9 @@ module unpack ( // also need to take into account possible zero/denorm/inf/NaN values // convert the half precsion exponent into quad precsion - XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {XLen3[`H_LEN-2], {`Q_NE-`H_NE{~XLen3[`H_LEN-2]&~XExpZero|XExpMaxE}}, XLen3[`H_LEN-3:`H_NF]}; - YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {YLen3[`H_LEN-2], {`Q_NE-`H_NE{~YLen3[`H_LEN-2]&~YExpZero|YExpMaxE}}, YLen3[`H_LEN-3:`H_NF]}; - ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {ZLen3[`H_LEN-2], {`Q_NE-`H_NE{~ZLen3[`H_LEN-2]&~ZExpZero|ZExpMaxE}}, ZLen3[`H_LEN-3:`H_NF]}; + XExpE = XOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {XLen3[`H_LEN-2], {`Q_NE-`H_NE{~XLen3[`H_LEN-2]}}, XLen3[`H_LEN-3:`H_NF]}; + YExpE = YOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {YLen3[`H_LEN-2], {`Q_NE-`H_NE{~YLen3[`H_LEN-2]}}, YLen3[`H_LEN-3:`H_NF]}; + ZExpE = ZOrigDenormE ? {1'b0, {`Q_NE-`H_NE{1'b1}}, (`H_NE-1)'(1)} : {ZLen3[`H_LEN-2], {`Q_NE-`H_NE{~ZLen3[`H_LEN-2]}}, ZLen3[`H_LEN-3:`H_NF]}; // extract the fraction and add the nessesary trailing zeros XFracE = {XLen3[`H_NF-1:0], (`Q_NF-`H_NF)'(0)}; diff --git a/pipelined/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv index 78ac99e50..5b1c22f91 100644 --- a/pipelined/src/generic/lzc.sv +++ b/pipelined/src/generic/lzc.sv @@ -3,11 +3,13 @@ module lzc #(parameter WIDTH=1) ( input logic [WIDTH-1:0] num, output logic [$clog2(WIDTH)-1:0] ZeroCnt ); +/* verilator lint_off CMPCONST */ logic [$clog2(WIDTH)-1:0] i; always_comb begin i = 0; - while (~num[WIDTH-1-i] & $unsigned(i) <= $unsigned(WIDTH-1)) i = i+1; // search for leading one + while (~num[WIDTH-1-(32)'(i)] & $unsigned(i) <= $unsigned(($clog2(WIDTH))'(WIDTH-1))) i = i+1; // search for leading one ZeroCnt = i; end +/* verilator lint_on CMPCONST */ endmodule diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 3e90aeaf4..cb214ce8f 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -1174,13 +1174,13 @@ end /////////////////////////////////////////////////////////////////////////////////////////////// // check if the non-fma test is correct - if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(UnitVal !== `CVTINTUNIT)) begin + if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin errors += 1; $display("There is an error in %s", Tests[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; end - + // TestFloat sets the result to all 1's when there is an invalid result, however in // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says // for an unsigned integer result 0 is also okay @@ -1470,7 +1470,7 @@ module readvectors ( Ans = TestVector[8]; end 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+3*(`H_LEN)-1:12+(`H_LEN)]}; + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+2*(`H_LEN)-1:12+(`H_LEN)]}; Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+(`H_LEN)-1:12]}; Ans = TestVector[8]; end From fa453986ad42a485e25db0adc26ba2b4a0bfcbc3 Mon Sep 17 00:00:00 2001 From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com> Date: Fri, 27 May 2022 20:59:23 +0000 Subject: [PATCH 25/28] plotting updates, normalization --- synthDC/ppaAnalyze.py | 119 +++++++++++++++++++++++++++++++----------- synthDC/ppaData.csv | 34 ++++++------ 2 files changed, 107 insertions(+), 46 deletions(-) diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py index d7f161802..14ab01ab4 100755 --- a/synthDC/ppaAnalyze.py +++ b/synthDC/ppaAnalyze.py @@ -5,6 +5,7 @@ from operator import index import subprocess import csv import re +from matplotlib.cbook import flatten import matplotlib.pyplot as plt import matplotlib.lines as lines import matplotlib.axes as axes @@ -29,7 +30,7 @@ def synthsintocsv(): ''' writes a CSV with one line for every available synthesis each line contains the module, tech, width, target freq, and resulting metrics ''' - + print("This takes a moment...") bashCommand = "find . -path '*runs/ppa*rv32e*' -prune" output = subprocess.check_output(['bash','-c', bashCommand]) allSynths = output.decode("utf-8").split('\n')[:-1] @@ -91,7 +92,7 @@ def cleanup(): def getVals(tech, module, var, freq=None): ''' for a specified tech, module, and variable/metric returns a list of values for that metric in ascending width order with the appropriate units - works at a specified target frequency or if none is given, uses the synthesis with the min delay for each width + works at a specified target frequency or if none is given, uses the synthesis with the best achievable delay for each width ''' if (var == 'delay'): @@ -101,11 +102,12 @@ def getVals(tech, module, var, freq=None): elif (var == 'lpower'): units = " (nW)" elif (var == 'denergy'): - units = " (pJ)" + units = " (nJ)" global widths metric = [] widthL = [] + if (freq != None): for oneSynth in allSynths: if (oneSynth.freq == freq) & (oneSynth.tech == tech) & (oneSynth.module == module): @@ -118,7 +120,7 @@ def getVals(tech, module, var, freq=None): m = 100000 # large number to start for oneSynth in allSynths: if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == module): - if (oneSynth.delay < m): + if (oneSynth.delay < m) & (1000/oneSynth.delay > oneSynth.freq): m = oneSynth.delay osdict = oneSynth._asdict() met = osdict[var] @@ -127,6 +129,8 @@ def getVals(tech, module, var, freq=None): if ('flop' in module) & (var == 'area'): metric = [m/2 for m in metric] # since two flops in each module + if (var == 'denergy'): + metric = [m*1000 for m in metric] # more practical units for regression coefs return metric, units @@ -177,9 +181,20 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): fullLeg = [] global techcolors global widths + + metrics = ['delay', 'area', 'lpower', 'denergy'] + ind1 = metrics.index(var) + techs = ['sky90', 'gf32', 'tsmc28'] + global norms + for combo in techcolors: tech, c, m = combo metric, units = getVals(tech, module, var, freq=freq) + + ind2 = techs.index(tech) + norm = norms[ind1][ind2] + metric = [m/norm for m in metric] # comment out to not normalize + if len(metric) == 5: xp, pred, leg = regress(widths, metric, combo, fits) fullLeg += leg @@ -191,10 +206,13 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn'): ax.set_xticks(widths) ax.set_xlabel("Width (bits)") - ax.set_ylabel(str.title(var) + units) + + ylabeldic = {"lpower": "Leakage Power", "denergy": "Dynamic Energy", "area": "Area", "delay": "Delay"} + + ax.set_ylabel(ylabeldic[var] + units) if singlePlot: - titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best delay)" + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best achievable delay)" ax.set_title(module + titleStr) plt.show() @@ -343,31 +361,69 @@ def squareAreaDelay(tech, mod, width): delaysL[ind] += [oneSynth.delay] areasL[ind] += [oneSynth.area] - fig = plt.figure() - ax = fig.add_subplot(111) + f, (ax1) = plt.subplots(1, 1) + ax2 = ax1.twinx() for ind in [0,1]: areas = areasL[ind] delays = delaysL[ind] - freqs = freqsL[ind] - + targets = freqsL[ind] + targets = [1000/f for f in targets] + if ('flop' in mod): areas = [m/2 for m in areas] # since two flops in each module - freqs, delays, areas = noOutliers(freqs, delays, areas) # comment out to see all syntheses + targets, delays, areas = noOutliers(targets, delays, areas) # comment out to see all + + if not ind: + achievedDelays = delays c = 'blue' if ind else 'green' - plt.scatter(delays, areas, color=c) - - legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), - lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] - - plt.legend(handles=legend_elements) + ax1.scatter(targets, delays, marker='^', color=c) + ax2.scatter(targets, areas, marker='s', color=c) - plt.xlabel("Delay Achieved (ns)") - plt.ylabel('Area (sq microns)') - plt.title(mod + '_' + str(width)) - ax.set_aspect(1./ax.get_data_ratio()) + bestAchieved = min(achievedDelays) + + legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='^', label='delay (timing achieved)'), + lines.Line2D([0], [0], color='green', ls='', marker='s', label='area (timing achieved)'), + lines.Line2D([0], [0], color='blue', ls='', marker='^', label='delay (timing violated)'), + lines.Line2D([0], [0], color='blue', ls='', marker='s', label='area (timing violated)')] + + ax2.legend(handles=legend_elements, loc='upper left') + + ax1.set_xlabel("Delay Targeted (ns)") + ax1.set_ylabel("Delay Achieved (ns)") + ax2.set_ylabel('Area (sq microns)') + ax1.set_title(mod + '_' + str(width)) + + squarify(f) + + xvals = np.array(ax1.get_xlim()) + frac = (min(flatten(delaysL))-xvals[0])/(xvals[1]-xvals[0]) + areaLowerLim = min(flatten(areasL))-100 + areaUpperLim = max(flatten(areasL))/frac + areaLowerLim + ax2.set_ylim([areaLowerLim, areaUpperLim]) + ax1.plot(xvals, xvals, ls="--", c=".3") + ax1.hlines(y=bestAchieved, xmin=xvals[0], xmax=xvals[1], color="black", ls='--') + plt.show() +def squarify(fig): + ''' helper function for squareAreaDelay() + forces matplotlib figure to be a square + ''' + w, h = fig.get_size_inches() + if w > h: + t = fig.subplotpars.top + b = fig.subplotpars.bottom + axs = h*(t-b) + l = (1.-axs/w)/2 + fig.subplots_adjust(left=l, right=1-l) + else: + t = fig.subplotpars.right + b = fig.subplotpars.left + axs = w*(t-b) + l = (1.-axs/h)/2 + fig.subplots_adjust(bottom=l, top=1-l) + def adprodpow(areas, delays, pow): ''' for each value in [areas] returns area*delay^pow helper function for freqPlot''' @@ -380,15 +436,15 @@ def adprodpow(areas, delays, pow): def plotPPA(mod, freq=None): ''' for the module specified, plots width vs delay, area, leakage power, and dynamic energy with fits - if no freq specified, uses the synthesis with min delay for each width + if no freq specified, uses the synthesis with best achievable delay for each width overlays data from both techs ''' fig, axs = plt.subplots(2, 2) oneMetricPlot(mod, 'delay', ax=axs[0,0], fits='cg', freq=freq) - oneMetricPlot(mod, 'area', ax=axs[0,1], fits='s', freq=freq) - oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits='s', freq=freq) - oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits='s', freq=freq) - titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best delay)" + oneMetricPlot(mod, 'area', ax=axs[0,1], fits='cl', freq=freq) + oneMetricPlot(mod, 'lpower', ax=axs[1,0], fits='cl', freq=freq) + oneMetricPlot(mod, 'denergy', ax=axs[1,1], fits='cl', freq=freq) + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best achievable delay)" plt.suptitle(mod + titleStr) plt.show() @@ -398,13 +454,16 @@ if __name__ == '__main__': Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy") techcolors = [['sky90', 'green', 'o'], ['tsmc28', 'blue', '^']] # add another list here for gf32 widths = [8, 16, 32, 64, 128] + norms = [[43.2, 15, 12.2], [1.96, .351, .252], [1.98, .3116, 1.09], [1, 1, 1]] # [sky, gf, tsmc][fo4, invx1area, leakage, energy] # synthsintocsv() # slow, run only when new synth runs to add to csv synthsfromcsv('ppaData.csv') # your csv here! ### examples - # oneMetricPlot('add', 'delay') - # freqPlot('sky90', 'comparator', 16) - # plotPPA('add') - squareAreaDelay('sky90', 'comparator', 16) \ No newline at end of file + # freqPlot('tsmc28', 'add', 16) + squareAreaDelay('sky90', 'add', 32) + squareAreaDelay('sky90', 'mult', 32) + squareAreaDelay('sky90', 'comparator', 32) + plotPPA('add') + plotPPA('comparator') \ No newline at end of file diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv index b5b0435cc..1c240ad24 100644 --- a/synthDC/ppaData.csv +++ b/synthDC/ppaData.csv @@ -13,6 +13,7 @@ flopenr,sky90,64,5619,0.204566,4385.500035,2100.0,4.961134631999999 comparator,sky90,128,10,0.842074,1997.240039,243.506,0.001300162256 add,sky90,8,6896,0.144869,331.240005,219.731,0.060410373 shiftleft,sky90,128,3484,0.313597,11188.660188,8590.0,2.418146467 +add,sky90,32,3120,0.320213,1107.40002,307.68,0.18700439200000005 flop,sky90,128,8476,0.070789,4264.959961,2070.0,3.6420232610000003 flopr,sky90,8,11879,0.11919,400.820003,214.285,0.662589129 add,tsmc28,64,3000,0.312507,227.052001,1070.0,0.0621263916 @@ -41,7 +42,6 @@ shiftleft,sky90,8,10222,0.097799,394.940007,435.049,0.06836150099999999 flopenr,sky90,64,4723,0.18608,4327.680086,2230.0,3.9400579199999997 flop,sky90,128,15539,0.070789,4264.959961,2070.0,6.676960058000001 alu,sky90,16,10000,0.304,3555.440059,2890.0,2.593728 -add,sky90,32,4320,0.254861,1716.960028,866.723,0.373881087 add,tsmc28,32,21130,0.080875,367.668003,1860.0,0.15414775 flop,sky90,8,14409,0.070789,266.559998,129.629,0.3870813309 comparator,sky90,64,4636,0.215691,2072.700029,1840.0,0.345752673 @@ -50,6 +50,7 @@ add,tsmc28,8,9092,0.108452,21.42,108.14,0.0057154204 add,sky90,16,4174,0.239287,549.780011,304.811,0.103371984 alu,sky90,16,3524,0.29417,3599.540061,2670.0,0.90839696 priorityonehot,sky90,8,21600,0.054084,157.780003,56.585,0.0190267512 +add,sky90,32,4368,0.268519,1731.660029,883.74,0.399824791 shiftleft,sky90,32,6375,0.159792,3330.040049,3530.0,0.627343392 priorityonehot,sky90,128,5185,0.274609,2437.260036,1210.0,0.250718017 add,tsmc28,128,6900,0.144862,733.320004,3010.0,0.22192858399999998 @@ -59,8 +60,8 @@ csa,sky90,128,16929,0.060643,4264.960083,3260.0,1.3935761400000002 shiftleft,sky90,32,6250,0.159977,2964.500038,3130.0,0.547281317 flopr,sky90,64,6988,0.11201,2728.319991,1360.0,2.4349853899999996 flop,sky90,64,19777,0.070789,2132.47998,1040.0,4.249180514000001 -add,sky90,32,3680,0.271527,1465.100024,591.825,0.289176255 priorityonehot,sky90,8,22800,0.054084,157.780003,56.585,0.0200976144 +add,sky90,32,3744,0.29863,1565.060028,830.413,0.31117246000000004 floprasync,sky90,8,15000,0.071444,362.600007,161.167,0.40944556400000004 mult,sky90,64,657,1.52205,69763.260863,23900.0,57.09818369999999 decoder,sky90,8,26064,0.037953,49.980001,39.023,0.0030893742000000003 @@ -145,7 +146,6 @@ add,sky90,16,4595,0.221986,817.320014,742.91,0.15871998999999998 flopenr,sky90,16,5285,0.169538,1127.000031,688.586,0.8848188220000001 priorityencoder,sky90,128,7500,0.113763,1058.400021,117.974,0.040499627999999996 priorityencoder,sky90,8,10131,0.104625,85.260002,26.481,0.0075225375 -add,sky90,32,4800,0.258491,1955.100033,1070.0,0.5043159410000001 add,tsmc28,8,7880,0.123121,20.538,106.097,0.0054665724 decoder,sky90,8,30334,0.032475,70.560001,88.439,0.006699592499999999 add,tsmc28,16,6443,0.138825,50.274,244.477,0.012882959999999999 @@ -190,6 +190,7 @@ mult,sky90,32,944,1.085045,32407.620517,26800.0,28.648443135 shiftleft,sky90,16,10769,0.131174,1153.460019,1350.0,0.26549617600000003 add,tsmc28,16,3000,0.32096,41.202,203.505,0.0116572672 add,tsmc28,128,8400,0.119042,1050.084009,4830.0,0.29831925200000003 +add,sky90,32,3978,0.280475,1768.90003,1000.0,0.34245997499999997 mult,sky90,32,4000,1.091389,31262.980534,24900.0,123.890113724 priorityencoder,sky90,8,9176,0.104625,85.260002,26.481,0.006821550000000001 floprasync,sky90,128,7500,0.071444,5785.920113,2580.0,3.3043564439999997 @@ -219,7 +220,6 @@ add,sky90,8,6355,0.157048,343.980005,234.605,0.064546728 csa,sky90,64,22360,0.060643,2195.200043,1740.0,0.937237565 priorityencoder,sky90,32,9184,0.111067,293.020006,53.82,0.015460526399999999 decoder,sky90,16,28542,0.039572,499.800013,875.782,0.058249984000000005 -add,sky90,32,4160,0.253175,2031.540036,1240.0,0.41900462499999996 shiftleft,sky90,8,11111,0.091007,491.960005,678.321,0.07371567000000001 alu,sky90,16,2073,0.481803,1688.540032,395.679,0.278963937 priorityonehot,sky90,128,3407,0.293484,1910.02003,670.082,0.107415144 @@ -253,6 +253,7 @@ add,tsmc28,8,7500,0.131988,20.916,106.321,0.0055698936 flopr,sky90,16,9317,0.10124,776.160012,486.897,0.78248396 priorityencoder,sky90,8,9749,0.104625,85.260002,26.481,0.0072505124999999995 csa,sky90,8,15971,0.062613,203.840004,117.131,0.0491950341 +add,sky90,32,4680,0.257118,1882.58003,1100.0,0.439157544 mult,sky90,128,584,1.712328,298800.044147,115000.0,257.92111732800004 priorityonehot,sky90,8,18400,0.054629,109.760001,31.371,0.009920626399999998 comparator,sky90,8,10909,0.11361,387.1,565.114,0.0965685 @@ -274,6 +275,7 @@ comparator,sky90,16,7200,0.15891,771.260013,1090.0,0.12331416 shiftleft,sky90,128,2968,0.33687,9142.420162,5660.0,1.7459972099999999 flop,sky90,32,13279,0.070789,1066.23999,518.516,1.4265894803 decoder,sky90,32,7500,0.115541,147.000003,15.758,0.006470296 +add,sky90,32,3588,0.278585,1182.860022,345.668,0.22342517000000003 decoder,sky90,128,7658,0.130462,549.78001,153.219,0.041225991999999996 mult,sky90,16,1122,0.891172,6478.780105,3540.0,4.677761828 shifter,sky90,16,5000,0.209586,2120.720031,2150.0,0.46528091999999993 @@ -307,8 +309,10 @@ flopr,sky90,128,15000,0.125811,5740.839996,3160.0,11.995198173 flopr,sky90,64,12112,0.101659,2816.520013,1550.0,3.8755460570000007 add,sky90,128,2615,0.390136,6662.040117,2450.0,1.2094216 flop,sky90,128,13561,0.070789,4264.959961,2070.0,5.826996535 +add,sky90,32,3900,0.280206,1679.720027,892.235,0.337928436 comparator,sky90,64,4727,0.225291,2499.000023,2710.0,0.465000624 add,sky90,8,7708,0.161451,407.680008,375.802,0.084923226 +add,sky90,32,4056,0.253823,1918.840034,1040.0,0.38657242900000005 add,tsmc28,16,16300,0.067336,189.63,1050.0,0.04902060799999999 priorityencoder,sky90,32,10000,0.111067,293.020006,53.82,0.016882183999999998 decoder,sky90,8,29973,0.032971,66.640001,78.184,0.0064062653 @@ -337,6 +341,7 @@ add,tsmc28,128,8232,0.121475,945.504008,4240.0,0.27429055 shiftleft,sky90,8,7500,0.132768,218.540002,147.871,0.034785216 priorityencoder,sky90,64,9782,0.112447,546.840011,77.149,0.028561538 add,tsmc28,64,7202,0.138773,305.424001,1310.0,0.09256159100000001 +add,sky90,32,3333,0.299576,1153.460022,384.333,0.20880447200000002 add,tsmc28,128,6720,0.148758,707.742004,2940.0,0.21629413200000003 mult,sky90,32,852,1.173643,23514.120391,12700.0,21.016425201 mult,sky90,32,741,1.349466,17389.120212,4650.0,10.286979318 @@ -380,7 +385,6 @@ priorityonehot,sky90,16,15000,0.086192,739.900005,1110.0,0.11920353600000001 shiftleft,sky90,128,3355,0.309977,11750.200195,9570.0,2.415650761 add,sky90,8,7437,0.151519,495.880011,457.493,0.09409329899999999 flop,sky90,64,14974,0.070789,2132.47998,1040.0,3.217289261 -add,sky90,32,3920,0.273454,2044.280039,1330.0,0.41154826999999994 csa,sky90,64,15971,0.062613,1630.720032,943.002,0.39320964 alu,sky90,16,2764,0.361248,2302.020041,1050.0,0.497438496 add,sky90,16,6307,0.225596,1023.12002,1010.0,0.281769404 @@ -419,7 +423,6 @@ add,tsmc28,8,14791,0.06639,27.468,134.31,0.007946883 flopenr,sky90,16,20000,0.189692,1098.580025,591.454,4.502529312 shiftleft,sky90,64,4348,0.23035,5490.940094,4500.0,1.0674419000000002 flop,sky90,8,14126,0.070789,266.559998,129.629,0.37948567120000004 -add,sky90,32,3200,0.312424,1121.120021,296.836,0.203700448 shiftleft,sky90,16,8154,0.128748,1062.320016,1070.0,0.17020485600000002 shiftleft,sky90,8,11333,0.092595,545.860006,815.115,0.089168985 priorityonehot,sky90,16,10667,0.09706,282.240005,85.616,0.025555897999999997 @@ -431,6 +434,7 @@ csa,sky90,16,17249,0.060643,533.12001,432.126,0.178714921 shiftleft,sky90,8,11778,0.091769,674.240011,1040.0,0.101037669 add,sky90,128,2718,0.407908,7287.280117,3350.0,1.463573904 floprasync,sky90,128,15000,0.071444,5785.920113,2580.0,6.602568704 +add,sky90,32,3666,0.278178,1498.420028,715.058,0.276508932 alu,sky90,32,3128,0.389409,5641.860104,2720.0,1.566592407 priorityonehot,sky90,32,7067,0.141491,1078.980015,1580.0,0.14389634700000004 floprasync,sky90,8,10000,0.071444,362.600007,161.167,0.2729375132 @@ -500,6 +504,7 @@ flopr,sky90,8,10947,0.11919,403.760003,218.217,0.60977604 add,sky90,16,10,2.032906,221.479998,55.29,0.0012902854382000001 flopr,sky90,128,10947,0.172973,5340.020018,2310.0,10.278747551999999 shiftleft,sky90,64,4261,0.234657,5289.060089,3950.0,0.980396946 +add,sky90,32,3822,0.282243,1657.18003,864.512,0.31752337500000005 priorityonehot,sky90,16,13333,0.077249,976.080015,1550.0,0.164694868 flopenr,sky90,128,6637,0.228828,8134.980007,3210.0,11.399295648 shiftleft,sky90,64,6087,0.227478,6715.940117,5940.0,1.7761482240000002 @@ -583,6 +588,7 @@ add,tsmc28,128,5040,0.197577,488.502002,2230.0,0.143045748 add,sky90,16,4144,0.240621,555.660011,274.571,0.092639085 alu,sky90,64,2409,0.452715,12468.540233,6180.0,2.755676205 add,sky90,16,2609,0.375085,405.720008,52.28,0.050598966499999995 +add,sky90,32,4134,0.25292,1966.860033,1110.0,0.40720119999999993 alu,sky90,128,2061,0.515343,27812.400516,13300.0,6.941154867 priorityonehot,sky90,64,4762,0.212289,1107.400013,650.606,0.09828980699999999 mult,sky90,8,1709,0.599356,2453.920037,2010.0,1.442649892 @@ -594,7 +600,6 @@ csa,sky90,32,16929,0.060643,1066.240021,827.644,0.348818536 csa,sky90,32,22360,0.060643,1097.600021,868.175,0.468891676 add,tsmc28,32,15394,0.081095,348.768003,1770.0,0.110694675 add,tsmc28,16,25000,0.066258,202.608001,1140.0,0.082027404 -add,sky90,32,2400,0.41509,958.440019,151.083,0.1286779 csa,sky90,16,12777,0.067531,329.280006,134.949,0.0528362544 decoder,sky90,8,39096,0.030694,184.240003,330.692,0.021700658 add,sky90,128,2359,0.423881,5520.340104,1490.0,0.846490357 @@ -615,7 +620,6 @@ alu,sky90,32,10000,0.384364,6083.84011,3640.0,5.60018348 flopr,sky90,32,20000,0.085865,1540.560029,1070.0,2.7735253650000002 flop,sky90,8,13279,0.070789,266.559998,129.629,0.35677656 csa,sky90,8,18207,0.060643,266.560005,213.306,0.0942877364 -add,sky90,32,6000,0.271774,1746.36003,955.901,0.5761608800000001 flop,sky90,64,13844,0.070789,2132.47998,1040.0,2.974482991 csa,sky90,128,16820,0.060643,4264.960083,3260.0,1.384661619 floprasync,sky90,8,8398,0.071444,362.600007,161.167,0.229263796 @@ -660,15 +664,16 @@ add,sky90,64,2788,0.358537,2637.180048,758.693,0.45928589700000005 flop,sky90,128,14126,0.070789,4264.959961,2070.0,6.069802805000001 flop,sky90,32,12996,0.070789,1066.23999,518.516,1.3962139204 decoder,sky90,8,35838,0.030694,237.160005,420.74,0.025291855999999998 -add,sky90,32,3840,0.291206,1547.420027,784.112,0.299650974 add,tsmc28,64,7500,0.133293,307.944001,1320.0,0.09437144399999998 alu,sky90,32,2398,0.416982,5257.700098,2000.0,1.094160768 add,tsmc28,128,7728,0.129394,854.910008,3690.0,0.25193011800000004 +add,sky90,32,3432,0.290785,1156.400022,335.133,0.20762049 flopenr,sky90,64,2892,0.298899,3245.75997,644.425,1.6744321980000003 priorityonehot,sky90,128,4000,0.253946,2661.680036,1330.0,0.210521234 floprasync,sky90,32,13997,0.071444,1446.480028,643.984,1.539332424 csa,sky90,32,16291,0.060643,1066.240021,825.615,0.33547707600000004 flopenr,sky90,64,4627,0.20887,3954.300054,1660.0,3.0662116000000004 +add,sky90,32,2340,0.42591,958.440019,152.032,0.12734709000000002 mux2,sky90,1,10,0.060639,6.86,1.19,3.1229084999999996e-07 flop,sky90,64,10000,0.070789,2132.47998,1040.0,2.1485735702000004 decoder,sky90,8,33883,0.030694,263.620004,439.421,0.027102802 @@ -695,6 +700,7 @@ decoder,sky90,16,25538,0.039572,265.580003,416.038,0.028729272 flopenr,sky90,64,5836,0.198621,4564.840035,2580.0,4.922821485 shiftleft,sky90,8,10444,0.095384,335.160004,328.601,0.060759608 add,sky90,8,5409,0.182541,209.720004,99.155,0.041436807000000006 +add,sky90,32,4212,0.276372,1701.280028,896.35,0.33496286399999997 add,tsmc28,32,1000,0.912322,67.157999,231.062,0.0220781924 flopenr,sky90,32,5764,0.185375,2024.679996,668.031,1.3873465 flop,sky90,32,15000,0.070789,1066.23999,518.516,1.6115399006000002 @@ -707,6 +713,7 @@ mult,sky90,16,976,1.024406,4960.760064,1320.0,2.087739428 add,tsmc28,16,6443,0.138825,50.274,244.477,0.012882959999999999 csa,sky90,128,18139,0.060643,4264.960083,3260.0,1.492970017 comparator,sky90,64,4364,0.229142,1709.120026,1020.0,0.276803536 +add,sky90,32,5460,0.27667,1690.500029,859.028,0.45456881 alu,sky90,32,2659,0.384337,6206.340103,3560.0,1.485846842 flopenr,sky90,64,5079,0.203824,4340.420085,2230.0,4.60947976 add,tsmc28,8,9056,0.108551,21.42,107.887,0.0057749132 @@ -718,7 +725,6 @@ decoder,sky90,8,24773,0.04026,44.100001,23.272,0.002604822 mult,sky90,8,1855,0.605444,2332.40004,1740.0,1.4470111599999997 flopenr,sky90,64,5013,0.228449,4007.220058,1760.0,3.779231807 add,sky90,8,25000,0.151154,660.520013,864.531,0.39103539800000003 -add,sky90,32,10,4.160501,456.679995,112.161,0.005429453805000001 shiftleft,sky90,16,7231,0.138234,1233.820018,1400.0,0.21619797600000001 add,tsmc28,64,9413,0.106226,423.108003,1900.0,0.12534668 decoder,sky90,8,10000,0.085629,37.240001,2.355,0.0012364827599999997 @@ -853,6 +859,7 @@ add,tsmc28,32,14791,0.079295,378.630002,1900.0,0.11220242500000001 decoder,sky90,8,25279,0.038956,48.020001,35.206,0.0031047931999999994 add,tsmc28,64,7732,0.129331,331.128002,1450.0,0.102042159 flopr,sky90,64,10714,0.17183,2815.540026,1390.0,5.43756035 +add,sky90,32,2631,0.379925,977.060019,169.107,0.140952175 priorityonehot,sky90,16,10000,0.099923,281.260004,117.94,0.02398152 mult,sky90,8,10,2.076433,1009.399998,211.637,0.005689426420000001 decoder,sky90,128,17868,0.101057,1072.12001,985.334,0.202922456 @@ -938,7 +945,6 @@ mult,sky90,8,1091,0.915221,1167.180013,211.892,0.30293815099999993 add,sky90,64,3636,0.330032,3266.340054,1220.0,0.79537712 flop,sky90,128,14692,0.070789,4264.959961,2070.0,6.313033809 add,tsmc28,8,15000,0.06579,28.728,137.18,0.008302698 -add,sky90,32,4080,0.256294,1991.360031,1240.0,0.408532636 shiftleft,sky90,16,10000,0.128994,1192.660017,1420.0,0.242379726 mult,sky90,64,10,14.7933,46798.920227,5460.0,2.7101325599999995 floprasync,sky90,16,14557,0.071444,723.240014,321.992,0.798601032 @@ -948,7 +954,6 @@ mult,sky90,128,10,29.334627,180734.540854,18000.0,22.264981893 flop,sky90,64,15539,0.070789,2132.47998,1040.0,3.3386216070000003 add,tsmc28,8,12074,0.081502,23.31,115.92,0.0062838042000000005 flopr,sky90,128,12811,0.174211,5123.439977,1890.0,10.893762252 -add,sky90,32,5000,0.2505,1933.540033,1030.0,0.4726935 mult,sky90,64,714,1.400528,87215.101373,43900.0,85.31176259200001 alu,sky90,64,2496,0.442869,12618.480223,6700.0,2.9570363129999997 priorityencoder,sky90,8,10323,0.104625,85.260002,26.481,0.0076690125 @@ -977,7 +982,6 @@ alu,sky90,64,2365,0.452964,12152.980222,6200.0,2.5982015040000004 priorityonehot,sky90,16,11111,0.089821,300.860005,305.978,0.029281646 comparator,sky90,32,5474,0.192304,1188.740012,1430.0,0.20691910400000002 flopenr,sky90,32,4803,0.217601,2179.52003,1080.0,2.520907585 -add,sky90,32,4240,0.268332,1829.660028,1090.0,0.373518144 csa,sky90,32,17568,0.060643,1066.240021,827.644,0.36203871 comparator,sky90,128,4000,0.268954,4027.800041,3660.0,0.679377804 decoder,sky90,8,31928,0.031295,106.82,190.81,0.010796775 @@ -988,7 +992,6 @@ add,tsmc28,32,8620,0.115079,146.538001,644.995,0.045571284000000004 flop,sky90,16,16104,0.070789,533.119995,259.258,0.8651406846 add,tsmc28,64,5043,0.178584,231.210001,1080.0,0.06107572799999999 priorityonehot,sky90,16,15556,0.088601,610.540002,811.656,0.097726903 -add,sky90,32,5600,0.254525,1871.800028,877.446,0.50039615 shiftleft,sky90,128,3871,0.303026,12747.840208,11600.0,3.235408602 flop,sky90,8,12996,0.070789,266.559998,129.629,0.34911011129999997 shiftleft,sky90,64,4435,0.24668,5129.320094,4030.0,1.0940258000000003 @@ -1084,7 +1087,6 @@ floprasync,sky90,128,13437,0.071444,5785.920113,2580.0,5.9146344279999985 shiftleft,sky90,128,3032,0.329767,9579.500162,6250.0,1.8898946769999998 flopr,sky90,32,12578,0.101547,1445.500023,882.979,2.039469948 alu,sky90,128,2217,0.514448,27540.940502,14000.0,7.25886128 -add,sky90,32,3760,0.278449,1689.520028,834.387,0.323279289 csa,sky90,128,16610,0.060643,4264.960083,3260.0,1.3673783640000001 floprasync,sky90,64,14557,0.071444,2892.960056,1290.0,3.203048852 flopenr,sky90,16,4228,0.180729,842.799992,176.142,0.3973688523 @@ -1093,6 +1095,7 @@ priorityonehot,sky90,32,7200,0.143094,1101.520018,1470.0,0.16956639 comparator,sky90,8,8545,0.116724,205.800003,165.947,0.041670467999999995 mult,sky90,128,528,1.893939,255011.682875,66500.0,175.06625146500002 shiftleft,sky90,64,10000,0.23373,6486.620108,6060.0,3.09762369 +add,sky90,32,2857,0.349019,998.620019,202.848,0.164736968 flop,sky90,16,13561,0.070789,533.119995,259.258,0.7285179146000001 priorityonehot,sky90,16,5000,0.196212,130.340003,29.8,0.005788254 mult,sky90,8,5000,0.552339,4261.040075,5050.0,5.394142674 @@ -1102,7 +1105,6 @@ comparator,sky90,16,8000,0.158838,801.640006,1190.0,0.15169029 flopenr,sky90,8,9518,0.148606,636.020015,366.016,0.9204655639999999 alu,sky90,16,3455,0.289435,3445.680058,2290.0,0.80289269 add,tsmc28,8,21130,0.050365,90.846,513.587,0.020700015 -add,sky90,32,4000,0.280842,1730.680031,849.828,0.358635234 priorityonehot,sky90,16,10222,0.097791,313.600004,134.808,0.026892525000000004 flopr,sky90,128,12112,0.177282,5399.800033,2390.0,11.989758942 flopr,sky90,8,12112,0.11919,400.820003,214.285,0.675533163 From d5c249bf71c0bc3cace64218bae3827a88ed7584 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Fri, 27 May 2022 14:37:10 -0700 Subject: [PATCH 26/28] unpacker adds 1 to denorm expoents --- .../build/Linux-x86_64-GCC/softfloat.a | Bin 513510 -> 571590 bytes pipelined/src/fpu/fcvt.sv | 6 +- pipelined/src/fpu/fma.sv | 67 ++++----- pipelined/src/fpu/fpu.sv | 9 +- pipelined/src/fpu/unpack.sv | 132 +++++++++--------- pipelined/testbench/testbench-fp.sv | 46 +++--- 6 files changed, 119 insertions(+), 141 deletions(-) diff --git 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