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Reduced size of preproc right shift

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David Harris 2022-12-30 06:47:40 -08:00
parent d2273e7037
commit 802c440254
1 changed files with 2 additions and 1 deletions
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pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -70,7 +70,8 @@ module fdivsqrtpreproc (
logic AsE, BsE, ALTBE, NegQuotE; logic AsE, BsE, ALTBE, NegQuotE;
logic [`XLEN-1:0] AE, BE; logic [`XLEN-1:0] AE, BE;
logic [`XLEN-1:0] PosA, PosB; logic [`XLEN-1:0] PosA, PosB;
logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX; logic [`DIVBLEN:0] ZeroDiff, IntBits;
logic [`LOGRK-1:0] RightShiftX;
// Extract inputs, signs, zero, depending on W64 mode if applicable // Extract inputs, signs, zero, depending on W64 mode if applicable
assign signedDiv = ~Funct3E[0]; assign signedDiv = ~Funct3E[0];