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More cache cleanup.

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This commit is contained in:
Ross Thompson 2022-02-09 19:29:15 -06:00
parent 754bd41fde
commit 7ff715f44f
1 changed files with 41 additions and 46 deletions
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7
pipelined/src/cache/cache.sv vendored
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@ -66,8 +66,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
localparam SETTOP = SETLEN+OFFSETLEN; localparam SETTOP = SETLEN+OFFSETLEN;
localparam TAGLEN = `PA_BITS - SETTOP; localparam TAGLEN = `PA_BITS - SETTOP;
localparam WORDSPERLINE = LINELEN/`XLEN; localparam WORDSPERLINE = LINELEN/`XLEN;
localparam LOGWPL = $clog2(WORDSPERLINE);
localparam LOGXLENBYTES = $clog2(`XLEN/8);
localparam FlushAdrThreshold = NUMLINES - 1; localparam FlushAdrThreshold = NUMLINES - 1;
logic [1:0] SelAdr; logic [1:0] SelAdr;
@ -80,11 +78,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
logic CacheHit; logic CacheHit;
logic FSMWordWriteEn; logic FSMWordWriteEn;
logic FSMLineWriteEn; logic FSMLineWriteEn;
logic [NUMWAYS-1:0] SRAMLineWayWriteEnable;
logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimWay;
logic [NUMWAYS-1:0] VictimDirtyWay; logic [NUMWAYS-1:0] VictimDirtyWay;
logic VictimDirty; logic VictimDirty;
logic [2**LOGWPL-1:0] MemPAdrDecoded;
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
logic [TAGLEN-1:0] VictimTag; logic [TAGLEN-1:0] VictimTag;
logic [SETLEN-1:0] FlushAdr; logic [SETLEN-1:0] FlushAdr;
@ -102,7 +98,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
logic SelFlush; logic SelFlush;
logic ResetOrFlushAdr, ResetOrFlushWay; logic ResetOrFlushAdr, ResetOrFlushWay;
logic [NUMWAYS-1:0] WayHitSaved, WayHitRaw; logic [NUMWAYS-1:0] WayHitSaved, WayHitRaw;
logic [LINELEN-1:0] ReadDataLineRaw, ReadDataLineSaved;
logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SelectedWay;
logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
logic [NUMWAYS-1:0] WriteWordWayEn, WriteLineWayEn; logic [NUMWAYS-1:0] WriteWordWayEn, WriteLineWayEn;
@ -184,7 +179,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// *** change to structural // *** change to structural
assign SelectedWay = SelFlush ? FlushWay : (FSMLineWriteEn ? VictimWay : WayHit); mux3 #(NUMWAYS) selectwaymux(WayHit, VictimWay, FlushWay, {SelFlush, FSMLineWriteEn}, SelectedWay);
assign SetValidWay = SetValid ? SelectedWay : '0; assign SetValidWay = SetValid ? SelectedWay : '0;
assign ClearValidWay = ClearValid ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0;
assign SetDirtyWay = SetDirty ? SelectedWay : '0; assign SetDirtyWay = SetDirty ? SelectedWay : '0;