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More cachefsm cleanup.

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This commit is contained in:
Ross Thompson 2022-02-07 11:16:20 -06:00
parent be67c4d559
commit 7f732eb571
1 changed files with 4 additions and 7 deletions
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11
pipelined/src/cache/cachefsm.sv vendored
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@ -140,10 +140,7 @@ module cachefsm
// *** Ross simplify: factor out next state and output logic // *** Ross simplify: factor out next state and output logic
always_comb begin always_comb begin
PreSelAdr = 2'b00; PreSelAdr = 2'b00;
//VDWriteEnable = 1'b0;
NextState = STATE_READY; NextState = STATE_READY;
CacheFetchLine = 1'b0;
CacheWriteLine = 1'b0;
save = 1'b0; save = 1'b0;
restore = 1'b0; restore = 1'b0;
case (CurrState) case (CurrState)
@ -209,7 +206,6 @@ module cachefsm
// read or write miss valid cached // read or write miss valid cached
else if((|RW) & ~CacheHit) begin else if((|RW) & ~CacheHit) begin
NextState = STATE_MISS_FETCH_WDV; NextState = STATE_MISS_FETCH_WDV;
CacheFetchLine = 1'b1;
end end
else NextState = STATE_READY; else NextState = STATE_READY;
end end
@ -228,7 +224,6 @@ module cachefsm
PreSelAdr = 2'b01; PreSelAdr = 2'b01;
if(VictimDirty) begin if(VictimDirty) begin
NextState = STATE_MISS_EVICT_DIRTY; NextState = STATE_MISS_EVICT_DIRTY;
CacheWriteLine = 1'b1;
end else begin end else begin
NextState = STATE_MISS_WRITE_CACHE_LINE; NextState = STATE_MISS_WRITE_CACHE_LINE;
end end
@ -328,7 +323,6 @@ module cachefsm
PreSelAdr = 2'b10; PreSelAdr = 2'b10;
if(VictimDirty) begin if(VictimDirty) begin
NextState = STATE_FLUSH_WRITE_BACK; NextState = STATE_FLUSH_WRITE_BACK;
CacheWriteLine = 1'b1;
end else if (FlushAdrFlag & FlushWayFlag) begin end else if (FlushAdrFlag & FlushWayFlag) begin
NextState = STATE_READY; NextState = STATE_READY;
PreSelAdr = 2'b00; PreSelAdr = 2'b00;
@ -354,7 +348,6 @@ module cachefsm
end end
STATE_FLUSH_CLEAR_DIRTY: begin STATE_FLUSH_CLEAR_DIRTY: begin
//VDWriteEnable = 1'b1;
PreSelAdr = 2'b10; PreSelAdr = 2'b10;
if(FlushAdrFlag & FlushWayFlag) begin if(FlushAdrFlag & FlushWayFlag) begin
NextState = STATE_READY; NextState = STATE_READY;
@ -413,6 +406,10 @@ module cachefsm
assign FlushAdrCntRst = (CurrState == STATE_READY & DoFlush); assign FlushAdrCntRst = (CurrState == STATE_READY & DoFlush);
assign FlushWayCntRst = (CurrState == STATE_READY & DoFlush) | (CurrState == STATE_FLUSH_INCR); assign FlushWayCntRst = (CurrState == STATE_READY & DoFlush) | (CurrState == STATE_FLUSH_INCR);
assign VDWriteEnable = (CurrState == STATE_FLUSH_CLEAR_DIRTY); assign VDWriteEnable = (CurrState == STATE_FLUSH_CLEAR_DIRTY);
assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss));
assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) |
(CurrState == STATE_FLUSH_CHECK & VictimDirty);
endmodule // cachefsm endmodule // cachefsm